Sources and References

• Sedra and Smith, Microelectronic Circuits (Oxford)
• Razavi, Fundamentals of Microelectronics (Wiley)
• Gray, Hurst, Lewis, and Meyer, Analysis and Design of Analog Integrated Circuits (Wiley)
• Neamen, Microelectronics: Circuit Analysis and Design (McGraw-Hill)
• Online: All About Circuits, Analog Devices tutorials, nanoHUB analog design modules

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Chapter 1: The MOSFET and Small-Signal Models

1.1 MOSFET Operating Regions

The metal-oxide-semiconductor field-effect transistor (MOSFET) operates in three regions depending on terminal voltages. Let \( V_{GS} \) be the gate-to-source voltage, \( V_{DS} \) drain-to-source, and \( V_t \) the threshold. For an n-channel device:

• Cut-off: \( V_{GS} < V_t \), negligible drain current.
• Triode: \( V_{DS} < V_{GS}-V_t \), current given by

\[ I_D = \mu_n C_{ox}\frac{W}{L}\left[ (V_{GS}-V_t)V_{DS} - \tfrac{1}{2}V_{DS}^{2} \right]. \]

• Saturation: \( V_{DS} \ge V_{GS}-V_t \), the channel pinches off at the drain end and

\[ I_D = \tfrac{1}{2}\mu_n C_{ox}\frac{W}{L}(V_{GS}-V_t)^{2}(1+\lambda V_{DS}). \]

The channel-length modulation parameter \( \lambda \) models the slight increase of \( I_D \) with \( V_{DS} \) arising from pinch-off point motion.

1.2 Biasing and Load Lines

An amplifier places the MOSFET in saturation far from the triode and cut-off boundaries. A simple resistive-drain bias with source resistor \( R_S \) provides negative feedback on the Q-point. Solving the quadratic bias equation simultaneously with the KVL

\[ V_{GS} = V_{GG} - I_D R_S \]

fixes the operating point. The load line is the drain-circuit constraint \( V_{DS} = V_{DD} - I_D R_D \). Its intersection with the device characteristic gives the DC operating point.

1.3 Small-Signal Model

Linearising around the Q-point yields a transconductance \( g_m = \partial I_D/\partial V_{GS} = \sqrt{2 \mu_n C_{ox}(W/L) I_D} \) and output resistance \( r_o = 1/(\lambda I_D) \). The small-signal model comprises a voltage-controlled current source \( g_m v_{gs} \) in parallel with \( r_o \), plus gate-source and gate-drain capacitances \( C_{gs}, C_{gd} \).

Chapter 2: Single-Stage Amplifiers

2.1 Common Source

The common-source amplifier delivers high voltage gain

\[ A_v = -g_m (r_o \parallel R_D), \]

with input at the gate and output at the drain. Output resistance is \( r_o \parallel R_D \); input impedance is ideally infinite. Source degeneration with \( R_S \) reduces gain to \( A_v \approx -g_m R_D/(1 + g_m R_S) \) but linearises the transfer characteristic and stabilises the Q-point.

2.2 Common Gate and Common Drain

The common-gate stage has low input impedance \( \approx 1/g_m \), high output impedance, and no sign inversion. It serves as a current buffer and in cascodes.

The common-drain (source follower) provides unity voltage gain and low output impedance \( \approx 1/g_m \), making it a voltage buffer that drives low impedance loads without loading upstream stages.

Chapter 3: Differential and Multistage Amplifiers

3.1 The Differential Pair

Two matched MOSFETs share a tail current source \( I_{SS} \). The differential input \( v_{id} = v_1 - v_2 \) divides the tail current between the devices. For small \( v_{id} \),

\[ \frac{I_{D1}-I_{D2}}{I_{SS}} = \frac{g_m v_{id}}{I_{SS}}. \]

The differential output is \( -g_m R_D v_{id} \). Common-mode signals, \( v_{ic} = (v_1+v_2)/2 \), experience gain limited by the tail source output impedance \( R_{SS} \), giving common-mode rejection ratio

\[ \mathrm{CMRR} = \frac{|A_{dm}|}{|A_{cm}|} \approx g_m R_{SS}. \]

3.2 Cascode and Current Mirrors

The cascode stacks a common-gate device on a common-source device, multiplying output resistance to \( \approx g_{m2} r_{o2} r_{o1} \) and boosting intrinsic gain. Current mirrors — basic, Widlar, Wilson, cascode — replicate a reference current for biasing tails and as active loads. An active load replaces \( R_D \) with a current source of impedance \( r_o \), raising single-stage gain to \( \approx g_m (r_{on} \parallel r_{op}) \), typically 40–60 dB.

Chapter 4: Feedback and Stability

4.1 Feedback Topologies

Feedback subtracts a fraction \( \beta \) of the output from the input. For ideal feedback around an amplifier with open-loop gain \( A \),

\[ A_f = \frac{A}{1 + A\beta}. \]

Four topologies — series-shunt, shunt-series, series-series, shunt-shunt — sense either voltage or current at the output and mix either voltage or current at the input. Each modifies input and output impedances by \( (1+A\beta) \) in the direction appropriate for the sensed and summed variable.

4.2 Stability and Compensation

Feedback around a multistage amplifier with several poles may oscillate. The Barkhausen criterion at oscillation requires \( |A\beta| = 1 \) with 180° of phase shift. Phase margin — the additional phase at the unity-gain frequency beyond 180° — should exceed 45° for step-response stability and 60° for small overshoot.

Dominant-pole (Miller) compensation inserts a capacitor across the high-gain stage, splitting its poles so that one becomes dominant and the other is pushed above the unity-gain frequency. The Miller effect multiplies the apparent capacitance at the input node by \( 1+|A| \), producing a low dominant pole with a modest physical capacitor.

Chapter 5: Oscillators and Waveform Circuits

5.1 Sinusoidal Oscillators

A sinusoidal oscillator is a positive-feedback loop whose Barkhausen criterion is satisfied exactly at one frequency. The Wien-bridge oscillator uses an RC bridge with oscillation frequency

\[ f_0 = \frac{1}{2\pi R C} \]

and loop gain set to three by a careful op-amp stage with diode or thermistor amplitude stabilisation.

LC oscillators (Colpitts, Hartley) use resonant tanks with tapped capacitors or inductors, operating well at RF where RC oscillators become impractical. Crystal oscillators leverage the very high \( Q \) of piezoelectric quartz to set frequency stabilities of a few parts per million.

5.2 Waveform Shaping

Schmitt triggers introduce hysteresis by placing positive feedback around a comparator, producing clean square-wave conversion of noisy inputs. Relaxation (astable) multivibrators combine a Schmitt trigger with an RC timing network to generate square waves; the period is

\[ T = 2 R C \ln\!\left(\frac{1+\beta}{1-\beta}\right), \]

where \( \beta \) is the positive-feedback fraction.

Chapter 6: Digital Building Blocks

6.1 The Transistor Switch

A MOSFET driven from cut-off to deep triode acts as a switch. On-resistance \( R_{on} = 1/[\mu_n C_{ox}(W/L)(V_{GS}-V_t)] \) is minimised by wide devices and high gate overdrive. Off-state leakage is dominated by subthreshold current, reverse-biased junction leakage, and gate tunneling.

6.2 CMOS Logic

Complementary MOS logic uses a pull-up network of pMOS devices and a pull-down network of nMOS devices that are strict complements, ensuring one and only one network conducts for any input combination. The CMOS inverter has static power approaching zero and rail-to-rail output swing. Switching power is

\[ P_{sw} = \alpha C_L V_{DD}^{2} f, \]

with \( \alpha \) activity factor, \( C_L \) load capacitance, and \( f \) clock frequency.

Propagation delay of an inverter driving a load \( C_L \) is approximately

\[ t_p = \frac{C_L V_{DD}}{2 I_{D,sat}}. \]

6.3 Delay and Sizing

Logical effort analysis predicts optimal gate sizing. For a chain of \( N \) stages, minimum delay occurs when each stage’s stage effort — the product of its logical effort and electrical effort — is equal, typically near 4. Thus large fan-outs should be staged through buffer chains rather than driven directly, minimising total delay.

Taken together, the progression from a single MOSFET through feedback amplifiers to CMOS logic illustrates a unifying principle: nonlinear devices, carefully biased and surrounded by negative feedback where linearity is needed and positive feedback where regeneration is wanted, produce the analog and digital building blocks of every modern electronic system.