Sources and References

• Plummer, Deal, and Griffin, Silicon VLSI Technology: Fundamentals, Practice and Modeling (Prentice Hall)
• Campbell, The Science and Engineering of Microelectronic Fabrication (Oxford)
• Jaeger, Introduction to Microelectronic Fabrication (Pearson)
• Ohring, Materials Science of Thin Films (Academic Press)
• Madou, Fundamentals of Microfabrication and Nanotechnology (CRC Press)
• Online: MIT OpenCourseWare 6.152J (Microelectronic Processing Technology), nanoHUB tutorials

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Chapter 1: Crystal Growth and Substrate Preparation

1.1 Single Crystal Silicon and the Czochralski Process

Nearly all integrated circuits begin with a boule of single-crystal silicon pulled from a melt by the Czochralski (CZ) technique. Polycrystalline silicon of high purity is melted in a fused-silica crucible near 1685 K, and a seed crystal of known orientation is dipped into the melt and slowly withdrawn while rotating. Surface tension and controlled thermal gradients promote solidification along the seed’s crystallographic axis, producing a cylindrical single-crystal boule.

The diameter of the growing crystal is governed by the balance between the pull rate \( v \), the thermal gradient at the solid–liquid interface, and the latent heat of fusion. For a steady-state diameter \( d \), the heat balance takes the form

\[ k_s A \frac{dT}{dz} = k_l A \frac{dT}{dz}\bigg|_{\text{liq}} + \rho_s L v A, \]

where \( k_s, k_l \) are thermal conductivities, \( \rho_s \) is the solid density, and \( L \) is the latent heat. Dopant incorporation follows the segregation coefficient \( k_0 = C_s/C_l \). For boron \( k_0 \approx 0.8 \); for phosphorus \( k_0 \approx 0.35 \). Axial concentration along the boule follows the Scheil equation

\[ C_s(x) = k_0 C_0 (1-x)^{k_0 - 1}, \]

with \( x \) the fraction solidified.

1.2 Float Zone and Wafer Fabrication

Higher-purity silicon for power devices is grown by the float-zone (FZ) method, in which an RF coil traverses a vertical rod, locally melting and refining the solid without crucible contact. Oxygen content in FZ material is orders of magnitude lower than in CZ silicon, improving carrier lifetime.

Boules are ground to a uniform diameter, sliced with diamond-wire saws, lapped, etched, and finally chemical-mechanically polished (CMP). CMP combines mechanical abrasion with chemical etching by a silica slurry in KOH to yield sub-nanometre roughness over a 300 mm wafer.

Chapter 2: Epitaxy and Ion Implantation

2.1 Homoepitaxy, Heteroepitaxy, and MBE

Epitaxy deposits a crystalline film onto a crystalline substrate, with the film inheriting the substrate lattice. Homoepitaxy uses the same material (Si on Si) to produce layers of controlled doping above a heavily doped substrate. Heteroepitaxy grows a different material (GaAs on Ge, SiGe on Si) and is constrained by lattice mismatch \( f = (a_f - a_s)/a_s \). Mismatch below roughly 1% yields pseudomorphic strained films up to a critical thickness \( h_c \) given by the Matthews–Blakeslee model

\[ h_c = \frac{b}{8\pi f (1+\nu)} \ln\left( \frac{h_c}{b} + 1 \right), \]

where \( b \) is the Burgers vector magnitude and \( \nu \) Poisson’s ratio.

Molecular-beam epitaxy (MBE) evaporates elemental sources in ultra-high vacuum (\(<10^{-10}\) Torr). Growth rates below one monolayer per second, combined with shutters controlling each beam, permit atomically abrupt interfaces used in quantum-well lasers and high-electron-mobility transistors.

2.2 Ion Implantation

Ion implantation introduces dopants by accelerating ionised atoms to 10–500 keV and driving them into the crystal. The projected range \( R_p \) and straggle \( \Delta R_p \) define a Gaussian concentration profile

\[ N(x) = \frac{\Phi}{\sqrt{2\pi}\,\Delta R_p} \exp\!\left( -\frac{(x-R_p)^2}{2\Delta R_p^2} \right), \]

where \( \Phi \) is dose per unit area. Energy loss combines nuclear (Lindhard–Scharff–Schiøtt) and electronic stopping.

Post-implant anneals (rapid thermal processing at 1000–1100 °C for seconds) repair damage and activate dopants. Transient enhanced diffusion from interstitial clusters must be modelled carefully.

Chapter 3: Oxidation and Diffusion

3.1 Deal–Grove Kinetics

Thermal oxidation of silicon forms SiO₂ via either dry (O₂) or wet (H₂O) ambients. The Deal–Grove model equates oxidant flux through the gas boundary layer, the oxide, and the reaction at the interface, producing

\[ x_{ox}^{2} + A\,x_{ox} = B(t + \tau), \]

with linear coefficient \( B/A \) and parabolic coefficient \( B \). For short times oxide grows linearly; for thick oxides growth is parabolic as diffusion limits the rate.

3.2 Dopant Diffusion

Dopants redistribute during high-temperature steps according to Fick’s second law

\[ \frac{\partial C}{\partial t} = \frac{\partial}{\partial x}\!\left( D\,\frac{\partial C}{\partial x} \right). \]

The diffusivity \( D = D_0 \exp(-E_a/k_B T) \) is strongly temperature-dependent. Two canonical solutions dominate process design: constant-surface-concentration (complementary error function) and constant-dose (Gaussian). Boron and phosphorus diffuse primarily by interstitial-substitutional exchange; arsenic diffuses by vacancy mechanisms and clusters at high concentration.

Chapter 4: Deposition Techniques

4.1 Physical Vapour Deposition

Physical vapour deposition (PVD) includes thermal evaporation, electron-beam evaporation, and sputtering. In DC sputtering, argon ions accelerated across a sheath bombard a target, ejecting atoms that traverse the plasma and condense on the substrate. The sputter yield \( Y \) depends on ion energy and target material; deposition rate scales as \( R \propto Y I/A \), with \( I \) the ion current and \( A \) the target area.

RF sputtering enables deposition of insulators by preventing target charging. Magnetron configurations confine electrons near the target using crossed E and B fields, raising plasma density and sputter rate.

4.2 Chemical Vapour Deposition

Chemical vapour deposition (CVD) grows films through surface reactions of gaseous precursors. Low-pressure CVD (LPCVD) operates at 0.1–1 Torr and provides excellent uniformity across batches. Plasma-enhanced CVD (PECVD) uses an RF plasma to activate precursors at lower temperature, useful after metallisation when thermal budget is limited.

For silane-based silicon nitride,

\[ 3\mathrm{SiH_4} + 4\mathrm{NH_3} \rightarrow \mathrm{Si_3N_4} + 12\mathrm{H_2}. \]

Atomic layer deposition (ALD) uses self-limiting surface reactions to build films one atomic layer per cycle, enabling conformal coatings with Ångström-level thickness control — critical for high-\( \kappa \) gate dielectrics such as HfO₂.

Chapter 5: Patterning — Lithography and Etching

5.1 Photolithography

A photolithographic cycle consists of spin coating a photoresist, soft baking, exposure through a reticle, post-exposure bake, development, and hard bake. Resist thickness from spin coating obeys

\[ t = \frac{K\,\eta^{\alpha}}{\omega^{\beta}}, \]

where \( \omega \) is angular velocity and \( \eta \) viscosity.

The resolution limit set by diffraction is

\[ R = k_1 \frac{\lambda}{\mathrm{NA}}, \]

with \( \mathrm{NA} \) the numerical aperture. Deep-UV systems (193 nm with immersion, \( k_1 \) down to 0.25) enable sub-40 nm features; extreme-UV at 13.5 nm pushes below 10 nm.

5.2 Etching and Micromachining

Wet etching of silicon in KOH is anisotropic: the (111) plane etches 50–100× more slowly than (100), producing pyramidal pits bounded by 54.7° sidewalls. This enables bulk micromachining of cantilevers and membranes.

Reactive ion etching (RIE) bombards the surface with energetic ions in a reactive plasma (SF₆, CF₄, Cl₂) to yield high-aspect-ratio, nearly vertical features. The Bosch process alternates SF₆ etching with C₄F₈ passivation to etch deep silicon trenches with selectivity over 100:1.

Spin coating and roll-to-roll printing extend patterning to flexible substrates for organic electronics and sensors.

Chapter 6: Process Integration, Yield, and Reliability

6.1 Device Scaling

Constant-field scaling (Dennard) shrinks lateral and vertical dimensions by \( 1/\kappa \), reduces supply voltage by \( 1/\kappa \), and keeps the electric field constant. Power density stays approximately constant while speed improves by \( \kappa \). The breakdown of Dennard scaling below 90 nm drove multi-gate FinFETs, strained silicon, and high-\( \kappa \) metal-gate stacks.

6.2 Yield

Defect-limited yield follows the Murphy model

\[ Y = \left( \frac{1 - e^{-A D_0}}{A D_0} \right)^2, \]

where \( A \) is die area and \( D_0 \) the defect density per unit area. Doubling die area severely reduces yield, motivating aggressive lithography reuse and die shrink.

6.3 Reliability Mechanisms

Key reliability mechanisms include electromigration in metal interconnects (Black’s equation \( \mathrm{MTTF} \propto J^{-n} \exp(E_a/k_B T) \)), time-dependent dielectric breakdown of thin oxides, hot-carrier injection, and negative-bias temperature instability. Process control, redundancy, and burn-in are essential to deliver parts meeting 10-year field lifetimes.

The full fabrication flow — from crystal growth to packaging — is a chain of interacting physical, chemical, and statistical processes. Rigorous modelling and control at each step are what turn a silicon boule into a functioning integrated circuit.