Sources and References

• Sedra, Smith, Carusone, and Gaudet, Microelectronic Circuits, 8th ed., Oxford University Press.
• Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill.
• Rabaey, Chandrakasan, and Nikolić, Digital Integrated Circuits: A Design Perspective, 2nd ed., Prentice Hall.
• Weste and Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed., Addison-Wesley.
• Baker, CMOS: Circuit Design, Layout, and Simulation, 4th ed., Wiley.

Chapter 1: The MOS Transistor

The metal-oxide-semiconductor field-effect transistor (MOSFET) is the fundamental device of modern integrated circuits. Its gate voltage modulates the conductivity of a thin channel between source and drain; four terminals (gate, source, drain, body) and a handful of physical parameters produce the device’s full behaviour over orders of magnitude of voltage and current.

1.1 Operating Regions

A long-channel NMOS transistor with threshold voltage \( V_T \) operates in cutoff when \( V_{GS} < V_T \), in triode when \( V_{GS} > V_T \) and \( V_{DS} < V_{GS} - V_T \), and in saturation when \( V_{DS} \geq V_{GS} - V_T \). The square-law model gives drain current

Here \( \mu_n C_{ox} \) is the process transconductance parameter, \( W/L \) is the aspect ratio, and \( \lambda \) captures channel-length modulation. PMOS devices follow the same form with reversed sign conventions and hole mobility.

1.2 Small-Signal Parameters

Linearizing about a bias point gives transconductance \( g_m = \sqrt{2 \mu_n C_{ox} (W/L) I_D} \), output resistance \( r_o = 1/(\lambda I_D) \), and body transconductance \( g_{mb} \). Parasitic capacitances — gate–source, gate–drain, junction — determine high-frequency behaviour and are included in small-signal models as appropriate.

1.3 Short-Channel Effects

Sub-100 nm processes depart from the square law: velocity saturation, drain-induced barrier lowering, mobility reduction under vertical field, and gate leakage each modify the transfer characteristic. Empirical models (BSIM) capture these for design; the square-law model suffices for first-cut hand analysis.

Chapter 2: Analog Building Blocks

2.1 Single-Stage Amplifiers

Three basic single-transistor amplifiers recur throughout analog design:

• Common-source: voltage-to-voltage gain \( A_v = -g_m (r_o \| R_D) \); input at gate, output at drain.
• Common-gate: current buffer with low input impedance \( 1/g_m \); used in cascodes and current mirrors.
• Source-follower (common-drain): voltage buffer with gain slightly less than one; low output impedance \( \approx 1/g_m \).

2.2 Current Mirrors and Active Loads

A simple current mirror copies a reference current by matching two transistors biased at the same \( V_{GS} \). Output resistance is \( r_o \); precision is limited by \( V_{DS} \) mismatch. Cascode mirrors boost output impedance to approximately \( g_m r_o^2 \), at the cost of reduced voltage headroom.

Active loads replace passive drain resistors with transistors operating as current sources, delivering very high small-signal load impedance without dropping the DC bias voltage. A single common-source stage with an active load has gain approaching the device intrinsic gain \( A_0 = g_m r_o \), often exceeding 100.

2.3 Differential Pairs

A differential pair is two matched transistors with a common-source bias current. Common-mode signals are rejected; differential signals produce \( g_m \Delta V/2 \) current at each output. Coupled with an active current-mirror load, the differential pair is the workhorse input stage of op-amps.

Chapter 3: Multistage Amplifiers and Cascodes

3.1 Cascading for Gain

Cascading amplifier stages multiplies voltage gains but introduces additional poles. Frequency compensation — pole splitting by a Miller capacitor, lead compensation, nested compensation — is essential to achieve the phase margin required for stable closed-loop operation. Feedback-amplifier theory (Bode, Black) quantifies the trade-off between gain, bandwidth, and stability.

3.2 Cascode Configurations

Cascodes stack a common-gate on top of a common-source stage. The common-gate device isolates the common-source output from high-frequency loading (reducing Miller effect) and delivers very high output impedance. Cascodes are ubiquitous in high-gain, high-speed analog design at the cost of reduced voltage headroom — a central concern in low-voltage processes.

3.3 Frequency Limitations

High-frequency response of an amplifier is set by pole locations, which in turn derive from device capacitances. The Miller effect multiplies gate-drain capacitance by \( 1 + |A_v| \), creating a dominant pole at the gate node of common-source stages. Unity-gain frequency \( f_T = g_m/(2\pi C_{GS}) \) is a figure of merit for the technology; circuit bandwidth is a fraction thereof determined by topology and compensation.

Chapter 4: Digital Transistor-Level Design

4.1 CMOS Inverter

The CMOS inverter pairs an NMOS pull-down with a PMOS pull-up. Static current is negligible; the structure consumes power only during transitions. Voltage transfer characteristic exhibits sharp transition near \( V_{DD}/2 \) when devices are sized symmetrically (\( (W/L)_P \approx 2.5 (W/L)_N \) to compensate for mobility difference). Noise margins \( NM_L \) and \( NM_H \) are read from the VTC.

Switching delay is \( t_p = (t_{pHL} + t_{pLH})/2 \) with

and power dissipation per transition is \( C_L V_{DD}^2 \) charged from the supply and dissipated through the on-device. Dynamic power at frequency \( f \) and activity \( \alpha \) is

4.2 Logic Gates and Styles

Static CMOS implements NAND, NOR, AND-OR-INVERT, and more complex functions by pulling the output high through a PMOS network and low through a complementary NMOS network. Delay and area scale with fan-in; four-input gates are a practical upper limit. Dynamic logic (domino, Np-CMOS) uses precharge and evaluate phases to reduce area at the cost of clocking discipline and noise sensitivity. Pass-transistor logic reduces transistor count for specific functions but loses signal swing and requires restoration.

4.3 Sequential Elements

Latches and flip-flops store state. A standard master–slave D flip-flop combines two transmission-gate latches clocked on opposite phases. Setup and hold times constrain data arrival; clock-to-Q delay propagates to downstream logic. Sequential design closes timing by balancing combinational delay against the clock period minus setup and clock-to-Q overhead.

Chapter 5: Arithmetic, Clocking, and Layout

5.1 Adders and Multipliers

Ripple-carry adders are compact but slow; carry-lookahead, carry-select, carry-save, and Kogge–Stone adders trade area for delay. Multipliers use partial-product arrays with Wallace or Dadda trees to reduce accumulation to a single carry-propagate add. Pipelining inserts registers in the combinational path to trade latency for throughput.

5.2 Clock Distribution

A modern digital chip’s clock network must deliver a coherent edge to every flip-flop. Clock trees and grids with buffers balance skew and jitter. Clock skew consumes timing budget; modest skew can be budgeted to relax setup or hold constraints. Gated clocks save dynamic power when blocks are idle.

5.3 Layout and Parasitics

The physical layout converts schematic intent into geometry on the chip. Wells, active, poly, contacts, and metal layers are drawn per process design rules that guarantee manufacturability. Parasitic resistance and capacitance of interconnect contribute to delay and power; at advanced nodes, wire delay often exceeds gate delay. Extracted simulation (post-layout) is mandatory before tape-out.

Matching and symmetry matter intensely in analog layout: common-centroid, interdigitated, and dummy-device techniques cancel gradients and edge effects. Shielding and guard rings isolate sensitive nodes from digital noise.

5.4 Design Flow and Tools

A practical integrated-circuit design flow includes schematic entry, SPICE simulation, layout in an industry-standard tool such as Cadence Virtuoso, design-rule checking, layout-versus-schematic verification, and post-layout simulation. This full loop connects circuit intent to a geometry that a foundry could fabricate.