Sources and References

• Valvano, Embedded Systems: Introduction to Arm Cortex-M Microcontrollers, 6th ed., Valvano.
• Wolf, Computers as Components: Principles of Embedded Computing System Design, 4th ed., Morgan Kaufmann.
• Stallings, Computer Organization and Architecture, 11th ed., Pearson.
• Patterson and Hennessy, Computer Organization and Design ARM Edition, Morgan Kaufmann.
• ARM, Cortex-M Series Technical Reference Manuals (current editions).

Chapter 1: Microprocessors and Microcontrollers

A microcontroller is a small computer integrated with the peripherals needed to interact with the physical world. For mechatronics the microcontroller is the bridge between sensors and actuators, between control algorithms and mechanical hardware. Fluent interfacing means understanding both sides: the digital side of buses, clocks, and interrupts, and the analogue side of timing, noise, and electrical compatibility.

1.1 Architecture

A typical Cortex-M microcontroller contains a 32-bit CPU, on-chip flash and SRAM, a clock tree, and a suite of peripherals on an internal bus matrix. The CPU executes instructions from flash using a three- or five-stage pipeline; Harvard-like bus organization allows simultaneous instruction fetch and data access. Registers R0–R12, stack pointer, link register, program counter, and program status register complete the user-visible state.

1.2 Memory Map

The 32-bit address space is partitioned into code, SRAM, peripherals, external RAM, external devices, and system regions. Peripherals are memory-mapped: reading or writing a specific address interacts with a hardware register. Bit-banding aliases single-bit operations onto word addresses, enabling atomic bit manipulation without read-modify-write hazards.

1.3 Clocks and Power

Clock trees derive core, bus, and peripheral clocks from crystal oscillators, internal RC oscillators, or PLLs. Lower clock frequencies reduce dynamic power \( P \propto C V^2 f \); sleep modes suspend clocks to idle blocks entirely. Embedded design balances processing requirements against battery life by selecting minimum adequate frequency and aggressive sleep scheduling.

Chapter 2: Synchronization and Data Flow

2.1 Polling Versus Interrupts

Polling continuously reads a status flag to detect an event. Interrupts let the hardware signal the CPU asynchronously; on interrupt, the CPU saves state and vectors to a service routine. Polling is simple but wastes CPU cycles; interrupts are efficient but require care with priority, nesting, and shared data.

2.2 Critical Sections and Concurrency

Data shared between an interrupt service routine (ISR) and main code must be protected. Disabling interrupts around a critical section guarantees atomicity but lengthens worst-case interrupt latency. Atomic bit-band accesses or load–linked/store–conditional operations (ARMv7-M LDREX/STREX) implement lock-free updates to small variables.

2.3 Direct Memory Access

DMA engines move data between memory and peripherals (or between memory regions) without CPU intervention. A DMA transfer is configured with source, destination, count, and channel priority; the peripheral issues a request, the DMA performs the transfer, and optionally an interrupt notifies the CPU at half- or full-buffer. DMA is essential for high-rate ADC, audio, and network peripherals.

Chapter 3: Digital Input and Output

3.1 Parallel GPIO

General-purpose I/O pins can be configured as input (floating, pull-up, pull-down) or output (push-pull, open-drain) with selectable slew rate and drive strength. Alternate functions route pin signals to specific peripherals. Reading the input data register reflects the instantaneous pin state; writing the output data register drives it.

3.2 Switch Debouncing and Key Matrices

Mechanical switches bounce for a few milliseconds when actuated. Debouncing combines hardware RC filtering with software timing: an input is considered changed only if it holds the new state for a debounce interval. Keypad matrices scan rows and columns to read many keys over few pins; the software returns the unique key at each intersection of driven row and sensed column.

3.3 Pulse-Width Modulation

PWM generates a square wave of fixed period and variable duty cycle, used to drive motors, LEDs, and valves. On the microcontroller, a timer counts up to a period value; a compare register sets the output high until the count reaches it, then low. Duty cycle is \( D = t_{on}/T \); average voltage applied to a load is \( D V_{cc} \) for a push-pull output, giving smooth linear control through a low-pass filter or an inductive load.

Chapter 4: Serial and Parallel Interfaces

4.1 Asynchronous Serial (UART)

A UART transmits framed bytes (start bit, 8 data bits, optional parity, 1 or 2 stop bits) at a shared baud rate. The receiver recovers timing from the start bit using an oversampling clock (typically 16×). Flow control is by software XON/XOFF or hardware RTS/CTS. UARTs interface to RS-232, RS-485, USB-to-UART bridges, and many radio modules.

4.2 SPI

The serial peripheral interface uses a clock (SCK), data lines (MOSI/MISO), and per-peripheral chip-select lines. Four modes (CPOL, CPHA) specify clock idle state and data-capture edge. Full-duplex transfer moves a byte in each direction per clock burst. SPI is simple and fast (tens of MHz) and is the usual choice for flash memory, ADCs, DACs, and sensor ICs.

4.3 I²C

Inter-integrated circuit is a two-wire (SDA, SCL) multi-drop bus with a simple addressing scheme and acknowledged byte transfers. Standard speeds are 100 kHz, 400 kHz, and 1 MHz; cable length is limited by line capacitance. Arbitration and clock stretching allow multi-master operation and slow-slave tolerance. I²C is ubiquitous for on-board sensors, EEPROMs, and PMICs.

4.4 CAN, USB, and Ethernet

Controller area network (CAN) is the dominant in-vehicle bus: differential signalling, arbitration by identifier priority, error detection, and robust recovery. USB and Ethernet interfaces appear on higher-end microcontrollers and carry much larger data rates at the cost of software stack complexity.

Chapter 5: Analogue Interfacing

5.1 Analogue-to-Digital Conversion

Successive-approximation ADCs are standard on microcontrollers, providing 10- to 16-bit conversion at up to a few megasamples per second. Sampling captures the input on a hold capacitor; the converter then finds the nearest code by binary search. Sample-and-hold droop, charge injection, and source impedance limit accuracy; anti-alias filtering matched to the Nyquist rate is mandatory.

Differential measurements reject common-mode noise; multiplexers allow a single ADC to serve many channels. DMA-driven, timer-triggered sequences acquire fixed sampling grids suitable for control loops.

5.2 Digital-to-Analogue Conversion

DACs produce analogue outputs from digital codes. R-2R ladder DACs sum weighted currents; sigma-delta DACs use oversampling and noise shaping for high resolution at moderate speed. Output buffers, reconstruction filters, and output drivers complete the chain.

5.3 Sensor and Actuator Conditioning

Real sensors produce small signals in the presence of noise; conditioning circuits amplify, filter, and level-shift into the ADC range. Instrumentation amplifiers reject common-mode noise; programmable-gain amplifiers adapt range. Actuator drivers supply the current and voltage required by motors and solenoids — MOSFET H-bridges for bidirectional DC motor drive, low-side drivers for solenoids, gate drivers for power devices.

Chapter 6: Privacy, Security, and Safety

6.1 Data Protection

Embedded systems increasingly handle sensitive data — personal health, location, credentials. Secure boot, encrypted firmware, and cryptographic operations (AES, SHA, ECC) are common requirements. Microcontrollers include hardware accelerators and true random-number generators for efficient implementation.

6.2 Threats and Countermeasures

Threats include firmware extraction, side-channel attacks (power analysis, electromagnetic emanation, timing), glitch injection, and network attacks. Countermeasures include readout protection, constant-time cryptographic code, redundant decision logic, and authenticated over-the-air updates. Regulatory frameworks (IEC 62443, automotive ISO/SAE 21434) increasingly mandate these measures.

6.3 Functional Safety

Functional safety (IEC 61508 and derivatives) requires systematic and random failure management for systems whose failure could endanger life or property. Techniques include redundant computation, watchdogs, flash and RAM integrity checks, and time-slot enforcement in real-time schedules. The mechatronics engineer working on automotive, medical, or industrial controls must design under both cybersecurity and safety regimes.