Sources and References

Primary texts: Digital Design by Mano and Ciletti (Pearson); Digital Design and Computer Architecture by Harris and Harris; Programmable Logic Controllers by Petruzella.

Supplementary texts: Embedded Systems: Introduction to the MSP432 Microcontroller by Valvano; FPGA Prototyping by SystemVerilog Examples by Chu; Industrial Automation: Hands-On by Lamb.

Online resources: MIT OpenCourseWare 6.111 Introductory Digital Systems Laboratory; Intel and AMD/Xilinx FPGA teaching labs; IEC 61131-3 standard for PLC programming; ARM Cortex-M reference documentation; STMicroelectronics and Microchip app notes.

Chapter 1: Number Systems and Boolean Algebra

1.1 Positional Number Systems

Binary, octal, decimal, and hexadecimal are positional systems with bases 2, 8, 10, and 16. Conversion among bases proceeds by repeated division or multiplication. Two’s-complement representation encodes signed integers: for an \( n \)-bit word the range is \( -2^{n-1} \) to \( 2^{n-1}-1 \).

1.2 Codes

Binary-coded decimal, Gray code, ASCII, and Unicode encode information for different purposes. Gray code flips only one bit between adjacent values, convenient for mechanical position encoders. Parity and Hamming codes detect or correct bit errors.

1.3 Boolean Algebra

Boolean variables take values 0 or 1. The operators AND, OR, and NOT satisfy identities such as \( A + \overline{A} = 1 \), \( A \cdot \overline{A} = 0 \), distribution \( A(B + C) = AB + AC \), and De Morgan’s laws

Canonical forms (sum-of-minterms and product-of-maxterms) provide unique representations of logic functions.

Chapter 2: Combinational Logic Design

2.1 Karnaugh Maps

Karnaugh maps geometrically visualise Boolean functions to identify minimal sum-of-products or product-of-sums forms. Grouping \( 2^k \) adjacent ones simplifies the expression. Don’t-care conditions expand grouping options. For many-variable functions, Quine–McCluskey tabulation or CAD tools automate minimisation.

2.2 Standard Building Blocks

Adders, subtractors, comparators, multiplexers, demultiplexers, encoders, and decoders are standard combinational modules. A ripple-carry adder has delay \( O(n) \); carry-lookahead and carry-save adders reduce it to \( O(\log n) \).

2.3 Arithmetic Logic Unit

An ALU integrates adders, logic operations, and control signals to perform arithmetic and logical operations on binary words. Status flags (zero, carry, overflow, negative) support conditional branching in a processor.

Chapter 3: Sequential Logic and State Machines

3.1 Latches and Flip-Flops

Storage elements are built from cross-coupled gates: SR latches, D latches, and edge-triggered D, JK, and T flip-flops. Setup time, hold time, and propagation delay constrain reliable operation. Metastability arises when inputs violate timing constraints; synchroniser chains mitigate it.

3.2 Finite-State Machines

A finite-state machine is a tuple \( (S, I, O, \delta, \lambda, s_0) \) of states, inputs, outputs, next-state and output functions, and an initial state. Moore machines output depends on state; Mealy machines include inputs in the output function. State diagrams, transition tables, and HDL descriptions are equivalent representations.

3.3 Registers and Counters

Shift registers move data serially; parallel-in-parallel-out registers hold data. Binary, decade, and ring counters sequence events. Synchronous designs use a global clock; asynchronous designs avoid it at the cost of race-condition risk.

Chapter 4: FPGA Implementation

4.1 FPGA Architecture

A field-programmable gate array consists of configurable logic blocks, routing fabric, I/O blocks, embedded memory, DSP slices, and clock networks. Each CLB contains look-up tables, flip-flops, and carry chains. Configuration loads from nonvolatile memory on power-up.

4.2 Hardware Description Languages

Verilog and VHDL describe hardware at behavioural, dataflow, and structural levels. Synthesis tools compile HDL into a gate-level netlist, place-and-route maps it to FPGA resources, and bitstream generation produces the configuration file. Simulation verifies behaviour before hardware deployment.

4.3 Testing and Timing

Functional simulation uses test benches with stimulus and expected responses. Static timing analysis confirms that the slowest path meets the clock period. Setup and hold checks, clock-domain crossing analysis, and metastability considerations ensure reliable operation.

Chapter 5: Microcontrollers

5.1 Architecture

A microcontroller integrates CPU, memory (flash, RAM), peripherals, and I/O on a single die. Common architectures include ARM Cortex-M, AVR, and PIC. Harvard architectures separate instruction and data memories; von Neumann architectures share them.

5.2 Programming

Microcontrollers are programmed in C or C++ with startup code that initialises stacks, vector tables, and clocks. Interrupts transfer control on peripheral events; service routines must be fast and minimise shared-state hazards. Real-time operating systems schedule tasks with priorities and deadlines.

5.3 Peripherals

General-purpose I/O, timers with input capture and PWM, analog-to-digital and digital-to-analog converters, and serial interfaces (UART, SPI, I\(^2\)C, CAN, USB) connect the microcontroller to the physical world. Direct memory access offloads data transfers from the CPU.

Chapter 6: Programmable Logic Controllers

6.1 Industrial Context

PLCs evolved from relay-logic panels in automotive manufacturing. They are ruggedised for temperature, vibration, and electrical noise, with deterministic scan cycles and hot-swappable modules. The international standard IEC 61131-3 defines five programming languages.

6.2 Ladder Logic

Ladder logic graphical representation mimics relay schematics. Rungs consist of contacts (inputs) and coils (outputs). Normally-open, normally-closed, latching, and one-shot instructions compose complex logic. Timers (on-delay, off-delay, retentive) and counters (up, down, up/down) support sequential operations.

6.3 Scan Cycle

A PLC executes a cyclic three-phase scan: input image update, logic execution, output image update. The scan time \( T_{scan} \) must be smaller than the fastest response time the control loop requires. Function blocks and structured text extend ladder logic for arithmetic, data handling, and communication.

6.4 Integration and Safety

Industrial systems combine PLCs, human-machine interfaces, supervisory control and data acquisition, and safety-related controllers. Safety PLCs following IEC 61508 and ISO 13849 use redundant and diverse channels to achieve specified safety integrity levels. Emergency stops, interlocks, and light curtains implement risk-reduction measures identified in hazard analyses.

Chapter 7: Interfacing Microcontrollers and PLCs

7.1 Signal Conditioning

Sensors output analog signals that require amplification, filtering, and isolation before digitisation. Strain gauges need bridge completion and instrumentation amplifiers; thermocouples need cold-junction compensation; 4–20 mA current loops reject noise over long cables.

7.2 Actuation

Outputs drive solenoid valves, motors, heaters, and indicators. Solid-state relays, optocouplers, and H-bridges interface low-power logic to industrial loads. Pulse-width modulation controls motor speed and lamp dimming with high efficiency.

7.3 Networking

Industrial Ethernet (PROFINET, EtherNet/IP, EtherCAT) and fieldbuses (Modbus, CANopen) connect distributed controllers. Deterministic networks support real-time control by bounding communication latency and jitter. Cybersecurity concerns increasingly shape industrial network design, motivating segmentation, authentication, and intrusion detection.