Sources and References

Primary textbook — A. S. Sedra, K. C. Smith, T. Chan Carusone, and V. Gaudet, Microelectronic Circuits, 8th ed., Oxford University Press, 2020. Supplementary texts — P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 5th ed., Wiley, 2009; B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017. Online resources — MIT OpenCourseWare 6.301 Solid-State Circuits; Stanford EE214B Analog Integrated Circuit Design lecture notes (B. Murmann).

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Chapter 1: Introduction and the Sample-and-Hold Amplifier

1.1 The Role of Analog Integrated Circuits

Modern electronic systems occupy a fundamentally mixed-signal world. Digital computation operates on discrete symbols, but the physical world presents continuous voltages, currents, temperatures, pressures, and optical intensities. Analog integrated circuits (ICs) form the essential interface layer: they amplify, filter, convert, and reference continuous-time signals before those signals are digitized, and they reconstruct analog waveforms from digital data streams.

CMOS technology has become dominant for analog IC design because it allows complete systems—amplifiers, filters, data converters, digital logic, and memory—to be integrated on a single die. The economics of scaling (smaller geometry, lower cost per transistor, higher density) continuously drive analog designers to adapt classical bipolar-era techniques to CMOS realities: limited supply voltage headroom, threshold-voltage variation, flicker (1/f) noise, and reduced intrinsic voltage gain per stage.

This course emphasizes CMOS with selective use of bipolar junction transistors (BJTs) for applications where their exponential I–V characteristic, high transconductance, or low flicker noise offer advantages unavailable in CMOS.

1.2 The Sample-and-Hold Amplifier

1.2.1 Function and Ideal Behavior

A sample-and-hold (S/H) amplifier captures (samples) an analog input voltage at a precise instant and holds that voltage constant for a subsequent processing interval—typically the conversion time of an analog-to-digital converter (ADC). Without a S/H, the ADC’s input would continue to change during conversion, introducing an aperture error.

The ideal S/H operates in two phases governed by a clock signal \(\phi\):

• Track (sample) phase \(\phi = 1\): The output follows the input continuously, \(V_{out}(t) = V_{in}(t)\).
• Hold phase \(\phi = 0\): The output is frozen at the value sampled at the falling edge of \(\phi\), \(V_{out}(t) = V_{in}(t_{s})\) for \(t > t_s\).

1.2.2 Non-Ideal Effects

Droop occurs during the hold phase when leakage currents \(I_{leak}\) (from the switch, the hold capacitor’s dielectric, or the input bias current of the output buffer) discharge the hold capacitor \(C_H\):

\[ \frac{dV_{hold}}{dt} = \frac{I_{leak}}{C_H} \]

Charge injection occurs when the sampling switch (a MOSFET) turns off: channel charge \(Q_{ch} = W L C_{ox}(V_{GS} - V_T)\) is injected partly onto \(C_H\), shifting the held voltage by \(\Delta V = Q_{ch}/(2C_H)\) (the factor of 2 arises from charge splitting between source and drain). Complementary switches (one NMOS, one PMOS) with matched widths partially cancel this error because their charge injections have opposite polarity.

Bottom-plate sampling is a widely used technique that eliminates signal-dependent charge injection. The hold capacitor’s bottom plate is disconnected from the virtual ground first, before the top-plate switch opens. Because the bottom-plate switch carries no signal current, its charge injection is signal-independent and produces only a fixed offset.

1.2.3 A Two-Times (×2) S/H Amplifier

A ×2 S/H amplifier simultaneously samples the input and amplifies it by a factor of 2, useful for pipeline ADC stages. One realization uses a switched-capacitor topology with two equal capacitors \(C\):

During the sampling phase, both capacitors charge to \(V_{in}\). During the hold/amplify phase, the capacitors are reconfigured in series with an inverting amplifier of gain \(-A\). With a virtual ground enforced by the feedback amplifier, the output voltage becomes \(V_{out} = 2V_{in}\) in the limit of large open-loop gain \(A\).

The closed-loop gain is:

\[ \frac{V_{out}}{V_{in}} = \frac{2A}{A + 2} \approx 2\left(1 - \frac{2}{A}\right) \text{ for } A \gg 1 \]

The gain error is \(-2/A\), motivating the need for high open-loop gain in the internal amplifier.

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Chapter 2: MOSFETs — Physical Operation and Small-Signal Models

2.1 MOSFET Operating Regions

The NMOS transistor is a four-terminal device: gate (G), drain (D), source (S), and bulk/body (B). With the bulk tied to the most negative supply (ground for NMOS, \(V_{DD}\) for PMOS), the device operates in three main regions.

2.1.1 Cutoff Region

When \(V_{GS} < V_{TN}\), no inversion layer forms and \(I_D \approx 0\) (neglecting subthreshold current for now). The device is “off.”

2.1.2 Triode (Linear) Region

When \(V_{GS} > V_{TN}\) and \(V_{DS} < V_{GS} - V_{TN} = V_{ov}\):

\[ I_D = \mu_n C_{ox} \frac{W}{L} \left[ (V_{GS} - V_{TN})V_{DS} - \frac{V_{DS}^2}{2} \right] \]

where \(\mu_n\) is electron mobility, \(C_{ox} = \varepsilon_{ox}/t_{ox}\) is the gate oxide capacitance per unit area, and \(W/L\) is the device aspect ratio. For small \(V_{DS}\), the device behaves as a voltage-controlled resistor with on-resistance:

\[ r_{DS,on} = \frac{1}{\mu_n C_{ox} (W/L)(V_{GS} - V_{TN})} \]

2.1.3 Saturation Region

When \(V_{GS} > V_{TN}\) and \(V_{DS} \geq V_{ov}\), the channel pinches off near the drain, and the drain current saturates:

\[ I_D = \frac{1}{2}\mu_n C_{ox} \frac{W}{L}(V_{GS} - V_{TN})^2 (1 + \lambda V_{DS}) \]

The term \(\lambda V_{DS}\) (channel-length modulation, with \(\lambda = 1/V_A\) where \(V_A\) is the Early voltage) accounts for the slight increase of \(I_D\) with \(V_{DS}\) due to effective channel-length shortening. In short-channel devices, \(V_A\) scales proportionally with \(L\).

2.2 Small-Signal Model

For small perturbations \(v_{gs}\), \(v_{ds}\), and \(v_{bs}\) about a DC operating point \((V_{GS}, V_{DS}, V_{BS})\), the drain current changes as:

\[ i_d = g_m v_{gs} + g_{mb} v_{bs} + \frac{v_{ds}}{r_o} \]

2.2.1 Transconductance

In saturation (ignoring \(\lambda\) for \(g_m\) calculation):

\[ g_m = \frac{\partial I_D}{\partial V_{GS}}\bigg|_{Q} = \mu_n C_{ox} \frac{W}{L} V_{ov} = \sqrt{2\mu_n C_{ox} \frac{W}{L} I_D} = \frac{2I_D}{V_{ov}} \]

These three equivalent forms are all useful. The second shows \(g_m \propto \sqrt{I_D}\) for fixed \(W/L\), while the third \(g_m = 2I_D/V_{ov}\) is a powerful design handle.

2.2.2 Output Resistance

\[ r_o = \frac{1}{\lambda I_D} = \frac{V_A}{I_D} \]

This finite output resistance limits the intrinsic voltage gain.

2.2.3 Body (Bulk) Transconductance

When the source is not connected to the bulk, changes in \(V_{BS}\) modulate the threshold voltage through the body effect:

\[ V_T(V_{SB}) = V_{T0} + \gamma\left(\sqrt{2\phi_f + V_{SB}} - \sqrt{2\phi_f}\right) \]

where \(\gamma = \sqrt{2q\varepsilon_{Si}N_A}/C_{ox}\) is the body-effect coefficient and \(\phi_f = (kT/q)\ln(N_A/n_i)\) is the Fermi potential. The body transconductance is:

\[ g_{mb} = \frac{\partial I_D}{\partial V_{BS}}\bigg|_{Q} = g_m \cdot \frac{\gamma}{2\sqrt{2\phi_f + V_{SB}}} = \eta g_m \]

where \(\eta \equiv g_{mb}/g_m \approx 0.1\text{–}0.2\) typically. In circuit analysis, the body effect manifests as an additional controlled current source \(g_{mb}v_{bs}\).

2.3 Weak Inversion (Subthreshold Operation)

Below threshold (\(V_{GS} < V_T\)), the channel is not fully inverted but minority carriers diffuse across the channel due to a concentration gradient. The drain current follows an exponential relationship:

\[ I_D = I_{D0} \frac{W}{L} \exp\!\left(\frac{V_{GS}}{nV_T}\right)\left(1 - e^{-V_{DS}/V_T}\right) \]

where \(n \approx 1.3\text{–}1.5\) is the subthreshold slope factor, \(V_T = kT/q \approx 26\) mV at room temperature, and \(I_{D0}\) is a process-dependent current. This exponential behavior is analogous to a BJT.

2.4 Intrinsic Voltage Gain

The intrinsic gain of a single common-source MOSFET stage (with no load resistance) is set by the product \(g_m r_o\):

\[ A_{v,intrinsic} = -g_m r_o = -\frac{2I_D}{V_{ov}} \cdot \frac{V_A}{I_D} = -\frac{2V_A}{V_{ov}} \]

Since \(V_A \propto L\) and \(V_{ov}\) is a design variable, intrinsic gain improves with longer channel length and lower overdrive. For a 0.18 µm process with \(V_A = 5\) V/µm \(\times\) 0.18 µm = 0.9 V and \(V_{ov} = 200\) mV: \(|A_v| = 2 \times 0.9/0.2 = 9\). This is much lower than BJT intrinsic gains (\(\sim 1000\times\)), motivating the widespread use of cascodes and multi-stage amplifiers in CMOS.

2.5 Transition Frequency

The transition frequency \(f_T\) (unity-current-gain frequency) measures the intrinsic speed of the transistor. It is defined as the frequency at which the short-circuit current gain \(|h_{21}|\) equals unity. In terms of device parameters:

\[ f_T = \frac{g_m}{2\pi(C_{gs} + C_{gd})} \approx \frac{g_m}{2\pi C_{gs}} \]

Since \(C_{gs} \approx \frac{2}{3}WLC_{ox}\) in saturation and \(g_m = \mu_n C_{ox}(W/L)V_{ov}\):

\[ f_T \approx \frac{\mu_n V_{ov}}{2\pi \cdot \frac{2}{3}L^2} = \frac{3\mu_n V_{ov}}{4\pi L^2} \]

This reveals that \(f_T \propto 1/L^2\), showing why technology scaling dramatically improves transistor speed. Higher overdrive also increases \(f_T\) at the cost of reduced \(g_m/I_D\) efficiency.

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Chapter 3: Single-Transistor Amplifiers, Current Mirrors, Differential Pairs, and Cascodes

3.1 Single-Transistor Amplifier Configurations

3.1.1 Common-Source Amplifier

With a resistive drain load \(R_D\) and ignoring body effect:

\[ A_v = -g_m(R_D \| r_o), \quad R_{in} = \infty \text{ (gate)}, \quad R_{out} = R_D \| r_o \]

For large signal gain, \(R_D\) should be large. However, large \(R_D\) limits the DC headroom (voltage drop \(I_D R_D\) must leave sufficient \(V_{DS}\) for saturation). An active load (current source) replaces \(R_D\) with a large small-signal resistance while presenting a controlled DC voltage drop.

3.1.2 Common-Gate Amplifier

3.1.3 Common-Drain (Source Follower)

\[ A_v = \frac{g_m R_S}{1 + (g_m + g_{mb})R_S} \approx \frac{g_m}{g_m + g_{mb}} = \frac{1}{1 + \eta} < 1 \]

The gain is slightly less than unity due to the body effect (since \(V_{BS}\) changes with the output). Output resistance is \(R_{out} \approx 1/(g_m + g_{mb})\), which is low—making the source follower useful as a buffer.

3.2 Current Mirrors

Current mirrors replicate a reference current to multiple branches with a fixed ratio. They are foundational to analog IC design.

3.2.1 Basic MOSFET Current Mirror

Transistor M1 is diode-connected (\(V_{GS1} = V_{DS1}\)), forcing it to set \(V_{GS}\). M2 shares the same \(V_{GS}\). If both transistors are identical and in saturation:

\[ I_{out} = I_{ref} \cdot \frac{(W/L)_2}{(W/L)_1} \]

The mirroring error arises from finite \(r_o\): as \(V_{DS2}\) differs from \(V_{DS1}\), channel-length modulation creates a systematic error \(\approx \lambda(V_{DS2} - V_{DS1})I_{ref}\).

3.2.2 Cascode Current Mirror

Adding cascode transistors M3 (diode-connected) and M4 forces \(V_{DS2} \approx V_{DS1}\), dramatically reducing the systematic error. The output resistance increases to approximately \(g_{m4}r_{o4}r_{o2}\).

3.2.3 Wilson Current Mirror

The Wilson mirror uses negative feedback through three transistors to force \(V_{DS1} \approx V_{DS2}\). Its output resistance is approximately \(\frac{g_{m3}r_{o3}r_{o1}}{2}\). The basic Wilson has a systematic error due to the asymmetric drain voltages of M1 and M2; the improved Wilson adds a fourth transistor to equalize them.

3.3 Differential Pair

The differential pair is the most important building block in analog IC design. An NMOS differential pair with tail current source \(I_{SS}\) and drain resistors \(R_D\):

3.3.1 Large-Signal Analysis

With input differential voltage \(v_{id} = V_{G1} - V_{G2}\):

\[ I_{D1} - I_{D2} = I_{SS} \tanh\left(\frac{v_{id}}{V_{ov}}\right) \quad \text{(approximate, exact for ideal square-law)} \]

The differential pair is linear for \(|v_{id}| \ll V_{ov}\) and saturates at \(\pm I_{SS}\) for large \(|v_{id}|\). The small-signal transconductance for the differential pair is \(G_m = g_{m1,2}\) where \(g_{m1,2}\) is the transconductance of each transistor at \(I_D = I_{SS}/2\).

3.3.2 Common-Mode Rejection Ratio

With a finite tail-current-source output resistance \(R_{SS}\), the common-mode gain is:

\[ A_{cm} = \frac{-R_D}{1/(g_m) + 2R_{SS}} \approx \frac{-R_D}{2R_{SS}} \]

The differential gain is \(A_{dm} = g_m R_D\) (with matched loads). The Common-Mode Rejection Ratio (CMRR) is:

\[ \text{CMRR} = \left|\frac{A_{dm}}{A_{cm}}\right| = \frac{g_m R_D}{R_D/(2R_{SS})} = 2g_m R_{SS} \]

With an ideal tail current source (\(R_{SS} \to \infty\)), CMRR \(\to \infty\). In practice, \(R_{SS} = r_{o,tail}\) of the tail transistor, giving CMRR \(\approx 2g_m r_{o,tail}\).

Mismatch in drain resistors (\(\Delta R_D\)) and transistor threshold voltages (\(\Delta V_T\)) create a finite CMRR even with ideal \(R_{SS}\):

\[ \text{CMRR}_{mismatch} \approx \frac{2R_D}{\Delta R_D} \text{ (from load mismatch)} \]

3.3.3 Input-Referred Offset

Threshold voltage mismatch \(\Delta V_T\) between M1 and M2, and \(W/L\) mismatch, produce an input-referred offset voltage. For a differential pair:

\[ V_{os} = \Delta V_T - \frac{V_{ov}}{2}\frac{\Delta(W/L)}{W/L} \]

Offset voltage is a critical specification; it can be trimmed using laser-trimmed resistors or switched-capacitor auto-zeroing.

3.4 Cascode Amplifiers

Cascoding dramatically increases output resistance and hence voltage gain, at the cost of reduced output voltage swing.

3.4.1 Telescopic Cascode

A cascode transistor M2 (common-gate) is stacked on M1 (common-source). The output resistance is:

\[ R_{out} \approx g_{m2}r_{o2}r_{o1} \]

This is a factor \(g_{m2}r_{o2} \gg 1\) larger than a single-transistor output resistance. The voltage gain becomes:

\[ A_v = -g_{m1}(g_{m2}r_{o2}r_{o1} \| R_{load}) \]

With a cascode active load (PMOS cascode), \(R_{load} \approx g_{mp}r_{op}^2\), and the gain becomes:

\[ |A_v| \approx g_{m1}(g_{mn}r_{on}^2 \| g_{mp}r_{op}^2) \]

This can approach 60–80 dB in modern processes.

Voltage swing penalty: Each stacked transistor requires a minimum \(V_{DS,sat} = V_{ov}\) for saturation. A telescopic cascode with NMOS cascode and PMOS cascode load requires at least \(4V_{ov}\) of drain-to-drain headroom, limiting its use in low-supply designs.

3.4.2 Folded Cascode

The folded cascode separates the input and cascode devices into different current branches, allowing the input NMOS pair to be cascoded by PMOS transistors operating from a PMOS current source. This consumes more power (two separate bias currents) but operates from a lower supply voltage since the input and cascode devices are no longer stacked.

Output resistance of the folded cascode (NMOS input, PMOS cascode):

\[ R_{out,n} \approx g_{m,cp}r_{o,cp}r_{o,n} \]

where subscripts \(n\) and \(cp\) denote the input NMOS and cascode PMOS devices.

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Chapter 4: Cascode OTAs and Gm-C Filters

4.1 Operational Transconductance Amplifiers

An Operational Transconductance Amplifier (OTA) is a voltage-input, current-output amplifier characterized by its transconductance \(G_m\). Unlike an op-amp, the OTA drives high-impedance (capacitive) loads; loading with a resistor degrades its behavior. The transfer function from input to output node is:

\[ V_{out} = G_m V_{in} \cdot Z_{out} \]

where \(Z_{out} = R_{out} \| \frac{1}{sC_L}\) for a capacitive load.

4.2 Telescopic Cascode OTA

The telescopic cascode OTA uses a differential pair with cascode active loads. Its key parameters:

• DC gain: \(A_0 = G_m R_{out}\) where \(R_{out} = g_{mp}r_{op}^2 \| g_{mn}r_{on}^2\)
• Dominant pole: \(\omega_{p1} = \frac{1}{R_{out}C_L}\)
• Unity-gain bandwidth: \(\omega_u = G_m / C_L\)
• Non-dominant poles: from internal cascode nodes, typically \(\omega_{p2} \approx g_{m,cascode}/C_{parasitic}\)

The gain-bandwidth product (GBW) of the OTA is:

\[ \text{GBW} = A_0 \cdot \omega_{p1} = G_m R_{out} \cdot \frac{1}{R_{out}C_L} = \frac{G_m}{C_L} \]

This is a fundamental result: GBW of a single-pole OTA equals \(G_m/C_L\) regardless of \(R_{out}\).

4.3 Folded-Cascode OTA

The folded-cascode OTA is the workhorse of low-voltage CMOS analog design. Its structure places the NMOS input pair and the PMOS cascode devices in parallel current paths. With bias current \(I_{bias}\) in the input pair and \(I_{cascode}\) in the PMOS bias branch:

\[ G_m = g_{m,input}, \quad R_{out} = r_{o,ncas} g_{m,ncas} r_{o,n} \| r_{o,pcas} g_{m,pcas} r_{o,p} \]

The slew rate (SR) for a capacitive load \(C_L\) is:

\[ SR = \frac{I_{max}}{C_L} = \frac{I_{SS}}{C_L} \]

where \(I_{SS}\) is the tail current. The SR sets the large-signal speed limit, independent of \(G_m\).

4.4 Gm-C Filters

Gm-C filters implement continuous-time filters using OTAs (as voltage-to-current converters) and capacitors. They avoid resistors, which are area-inefficient and poorly matched in CMOS. The basic Gm-C integrator implements:

\[ V_{out}(s) = \frac{G_m}{sC} V_{in}(s) \quad \Rightarrow \quad H(s) = \frac{G_m}{sC} \]

This is an ideal lossless integrator with a unity-gain frequency (integrator frequency) of:

\[ \omega_i = \frac{G_m}{C} \]

4.4.1 Second-Order Gm-C Filter (Biquad)

A second-order lowpass filter can be realized with two integrators in a loop:

\[ H(s) = \frac{G_{m1}G_{m2}/(C_1 C_2)}{s^2 + s\frac{G_{m3}}{C_1} + \frac{G_{m1}G_{m2}}{C_1 C_2}} \]

Comparing to the standard form \(H(s) = \omega_0^2 / (s^2 + s\omega_0/Q + \omega_0^2)\):

\[ \omega_0 = \sqrt{\frac{G_{m1}G_{m2}}{C_1 C_2}}, \quad Q = \frac{\sqrt{G_{m1}G_{m2}C_1 C_2}}{G_{m3}C_1} \]

The tuning of \(\omega_0\) and \(Q\) is achieved by adjusting bias currents (which control \(G_m\)), making Gm-C filters electronically tunable. This is essential for compensating process and temperature variations.

4.4.2 Practical Limitations

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Chapter 5: Current and Voltage References

5.1 The Need for Stable References

Accurate biasing requires currents and voltages that are independent of supply voltage \(V_{DD}\), temperature \(T\), and process variation. A voltage reference provides a stable DC voltage; a current reference provides a stable DC current.

5.2 The PTAT Current Reference

A Proportional To Absolute Temperature (PTAT) current has \(I \propto T\). Using two BJTs (or MOSFET diodes in weak inversion) operating at different current densities:

\[ V_{BE1} - V_{BE2} = V_T \ln\frac{I_1/I_{S1}}{I_2/I_{S2}} = V_T \ln(N) = \frac{kT}{q}\ln N \]

where \(N\) is the ratio of emitter areas. This PTAT voltage developed across a resistor \(R\) produces:

\[ I_{PTAT} = \frac{V_T \ln N}{R} \]

The temperature coefficient is \(\partial I_{PTAT}/\partial T = (k/q)\ln(N)/R\), which is positive (PTAT).

5.3 The Bandgap Reference

The bandgap voltage reference combines a PTAT voltage with a Complementary To Absolute Temperature (CTAT) voltage to produce a temperature-independent reference near the silicon bandgap voltage \(V_{go} \approx 1.205\) V.

A BJT’s \(V_{BE}\) is CTAT (decreasing with temperature at \(\approx -2\) mV/°C). The output reference voltage is:

\[ V_{ref} = V_{BE} + K \cdot \Delta V_{BE} = V_{BE} + K V_T \ln N \]

At the zero-TC point, \(\partial V_{ref}/\partial T = 0\):

\[ K = \frac{|\partial V_{BE}/\partial T|}{V_T/T \cdot \ln N} = \frac{0.002}{26\times10^{-3}/300 \cdot \ln N} \]

For \(N = 8\), \(K \approx 10.5\). The resulting \(V_{ref} \approx 1.25\) V \(\approx V_{go}\)—the silicon bandgap.

5.4 Supply-Independent Biasing

A self-biased current reference generates its own bias current, breaking the dependence on \(V_{DD}\). The classic Widlar self-biased reference:

Transistors M1 and M2 form a feedback loop. M1 acts as a diode-connected device setting the current, and M2 (with source degeneration resistor \(R_S\)) forces:

\[ V_{GS1} = V_{GS2} + I_{ref} R_S \]

This has two stable operating points: the desired operating point and the trivial zero-current solution. A startup circuit (typically a weak PMOS pulling the circuit above threshold) ensures the desired point is reached at power-on.

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Chapter 6: Feedback and Stability

6.1 Feedback Fundamentals

In a feedback amplifier, a fraction \(\beta\) of the output is subtracted from the input:

\[ A_f = \frac{A}{1 + A\beta} \]

where \(A\) is the open-loop gain and \(A\beta\) is the loop gain \(T\). Negative feedback (\(T > 0\)) reduces gain by \((1+T)\) but improves bandwidth, reduces distortion, and controls impedance levels.

Effect on bandwidth: If the open-loop amplifier has a single-pole response \(A(s) = A_0/(1 + s/\omega_p)\), the closed-loop bandwidth expands to \(\omega_{p,cl} = \omega_p(1+T)\), and the gain-bandwidth product is preserved: \(A_f \cdot \omega_{p,cl} = A_0 \omega_p = \text{GBW}\).

6.1.1 Feedback Topologies

Four feedback topologies exist based on the type of output quantity sampled and the type of error signal formed:

Topology	Output sampled	Input summed	Effect on \(R_{in}\)	Effect on \(R_{out}\)
Series-shunt (voltage amp)	Voltage	Voltage (series)	Increases by \((1+T)\)	Decreases by \((1+T)\)
Shunt-shunt (transresistance)	Voltage	Current (shunt)	Decreases by \((1+T)\)	Decreases by \((1+T)\)
Series-series (transconductance)	Current	Voltage (series)	Increases by \((1+T)\)	Increases by \((1+T)\)
Shunt-series (current amp)	Current	Current (shunt)	Decreases by \((1+T)\)	Increases by \((1+T)\)

6.2 Stability Analysis: Bode Plots and Phase Margin

For a feedback system, stability requires that the loop gain \(T(j\omega) = A(j\omega)\beta\) does not satisfy the Barkhausen criterion for oscillation: \(|T| = 1\) and \(\angle T = -180°\).

Phase margin (PM) is defined as:

\[ \text{PM} = 180° + \angle T(j\omega_c) \]

where \(\omega_c\) is the gain crossover frequency (\(|T(j\omega_c)| = 1\). A PM \(> 0°\) implies stability; PM \(> 45°\) is typically required for acceptable transient response. A PM of 60° corresponds to approximately no overshoot in closed-loop step response.

Gain margin (GM) is the reciprocal of \(|T|\) at the phase crossover frequency \(\omega_{pc}\) (where \(\angle T = -180°\):

\[ \text{GM (dB)} = -20\log_{10}|T(j\omega_{pc})| \]

A GM \(> 10\) dB is typical for robust designs.

6.2.1 Bode Plot Construction for a Two-Pole System

For a two-pole open-loop gain:

\[ A(s) = \frac{A_0}{(1 + s/\omega_{p1})(1 + s/\omega_{p2})} \]

The magnitude plot rolls off at -20 dB/decade after \(\omega_{p1}\) and -40 dB/decade after \(\omega_{p2}\). The phase approaches \(-180°\) asymptotically. If the unity-gain frequency \(\omega_u = A_0 \omega_{p1}\) (assuming \(\omega_{p1} \ll \omega_{p2}\)) satisfies \(\omega_u \ll \omega_{p2}\):

\[ \text{PM} \approx 90° - \arctan\!\left(\frac{\omega_u}{\omega_{p2}}\right) \]

For PM = 45°: \(\omega_u = \omega_{p2}\). For PM = 60°: \(\omega_u = \omega_{p2}/\sqrt{3}\).

This directly motivates frequency compensation: we must push \(\omega_{p2}\) above \(\omega_u\), or push \(\omega_{p1}\) well below \(\omega_{p2}\), to achieve the required phase margin.

6.3 Root Locus Analysis

The closed-loop poles as a function of loop gain \(T\) trace the root locus. For a two-pole forward path with both poles on the negative real axis at \(-\omega_{p1}\) and \(-\omega_{p2}\), increasing \(T\) from 0 causes the closed-loop poles to:

1. Begin at the open-loop poles \(-\omega_{p1}\) and \(-\omega_{p2}\).
2. Move toward each other on the real axis.
3. Collide at \(-(\omega_{p1}+\omega_{p2})/2\) and then split into a complex conjugate pair.
4. Move into the right-half plane if the system is unstable.

The natural frequency of the complex pair is \(\omega_n = \sqrt{\omega_{p1}\omega_{p2}}\) and the damping ratio \(\zeta = (\omega_{p1}+\omega_{p2})/(2\omega_n)\). For PM \(\approx 60°\), \(\zeta \approx 0.7\) (critically damped), giving clean transient response with minimal overshoot.

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Chapter 7: CMOS Two-Stage OTA and Frequency Compensation

7.1 The Two-Stage CMOS OTA

The two-stage OTA solves a fundamental tension: the first stage provides high gain using a cascode or differential pair, while the second stage (a common-source amplifier) extends the output swing to within \(V_{DS,sat}\) of both rails.

A classic two-stage OTA (Razavi, Gray-Hurst-Lewis-Meyer) has:

• Stage 1: NMOS differential pair (M1, M2) with PMOS current-mirror load (M3, M4). Gain: \(A_1 = g_{m1}(r_{o2}\|r_{o4})\).
• Stage 2: PMOS common-source amplifier (M5) with NMOS current-source load (M6). Gain: \(A_2 = g_{m5}(r_{o5}\|r_{o6})\).

Total DC gain:

\[ A_0 = A_1 A_2 = g_{m1}(r_{o2}\|r_{o4}) \cdot g_{m5}(r_{o5}\|r_{o6}) \]

7.2 Miller Compensation

Without compensation, the two-stage OTA has two poles of comparable magnitude, giving poor phase margin. Miller compensation adds a capacitor \(C_c\) from the output of stage 2 back to the output of stage 1 (the input of stage 2).

7.2.1 Effect of Miller Capacitor

The Miller effect reflects \(C_c\) to the input of stage 2 with an apparent capacitance \(C_c(1 + |A_2|)\), creating a large capacitance at the first-stage output node. This:

1. Splits the poles: The dominant pole \(\omega_{p1}\) moves to very low frequencies (pole splitting), while the non-dominant pole \(\omega_{p2}\) moves to higher frequencies.
2. Reduces bandwidth at the first stage output.
3. Creates a right-half-plane zero due to the feedforward path through \(C_c\).

7.2.2 Pole-Zero Analysis

Using nodal analysis with Miller compensation, the approximate transfer function is:

\[ A(s) \approx \frac{A_0 \left(1 - s\frac{C_c}{g_{m5}}\right)}{(1 + s/\omega_{p1})(1 + s/\omega_{p2})} \]

where:

\[ \omega_{p1} \approx \frac{1}{A_2 R_1 C_c} = \frac{g_{m5}}{A_0 C_c}, \quad \omega_{p2} \approx \frac{g_{m5}}{C_L + C_c} \approx \frac{g_{m5}}{C_L} \]

and the right-half-plane (RHP) zero is:

\[ \omega_z = \frac{g_{m5}}{C_c} \]

7.2.3 Unity-Gain Bandwidth of the Two-Stage OTA

The unity-gain bandwidth (assuming \(\omega_{p1}\) is the dominant pole and ignoring the RHP zero):

\[ \text{GBW} = A_0 \cdot \omega_{p1} = \frac{g_{m1}}{C_c} \]

This elegant result shows that GBW is set by the first-stage transconductance and the compensation capacitor, independent of the DC gain. The designer can independently choose \(g_{m1}/C_c\) for bandwidth and increase \(A_0\) by lengthening transistors (increasing \(r_o\)).

7.2.4 Slew Rate and Settling Time

The slew rate of the two-stage OTA is set by the output current capability of the first stage into the compensation capacitor:

\[ SR = \frac{I_{SS}}{C_c} \]

where \(I_{SS}\) is the tail current of the differential pair. For a step input large enough to fully steer \(I_{SS}\), the slew rate limits the large-signal speed.

After slewing, the amplifier enters linear settling governed by the closed-loop bandwidth. The settling time to an accuracy of \(\epsilon\) (as a fraction of the step) is:

\[ t_{settle} \approx \frac{\ln(1/\epsilon)}{\omega_{cl}} = \frac{\ln(1/\epsilon)}{\beta \cdot \text{GBW}} \]

For 12-bit settling (\(\epsilon = 1/4096\)) with closed-loop feedback factor \(\beta = 1\): \(t_{settle} \approx 8.3/\text{GBW}\).

7.2.5 Design Procedure for the Two-Stage OTA

A systematic design flow:

1. Specify: \(A_0\), GBW, PM, \(V_{DD}\), power budget, load \(C_L\).
2. Choose GBW and PM: Select \(\omega_{p2}/\text{GBW} \geq 2.2\) for PM \(\geq 60°\).
3. Set \(g_{m5}/C_L \geq 2.2 \cdot \text{GBW}\): Determines \(g_{m5}\) from \(C_L\).
4. Set \(g_{m1}/C_c = \text{GBW}\): Determines \(g_{m1}\) and \(C_c\) (choose \(C_c \geq 0.22 C_L\) as a rule of thumb).
5. Set bias currents: \(I_{SS} = g_{m1}V_{ov1}\), \(I_{D5} = g_{m5}V_{ov5}/2\).
6. Size transistors: \(W/L = g_m^2/(2\mu C_{ox} I_D)\).
7. Set \(A_0\): Increase \(L\) for larger \(r_o\), or use cascode in stage 1.
8. Add nulling resistor \(R_z = 1/g_{m5}\) (MOSFET in triode).

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Chapter 8: Power Amplifiers and Output Stages

8.1 Classification of Power Amplifiers

Power amplifiers are classified by the fraction of the signal cycle during which the output transistor conducts:

Class	Conduction angle	Efficiency	Linearity
A	360° (full cycle)	\(\leq 25\%\) (resistive load), \(\leq 50\%\) (inductive)	Excellent
B	180° (half cycle)	\(\leq 78.5\%\)	Crossover distortion
AB	Between 180° and 360°	50–78%	Good (bias reduces crossover)
C	\(< 180°\)	High (\(> 78\%\))	Poor (tuned loads only)
D	Switching	\(> 90\%\)	Requires reconstruction filter

8.2 Class A Output Stage

A class A source follower: the output transistor conducts for the full cycle. The quiescent current \(I_Q\) must exceed the peak output current \(I_{peak}\) to avoid clipping:

\[ I_Q \geq \frac{V_{o,max}}{R_L} \]

Maximum efficiency: \(\eta = P_{load}/P_{supply} \leq 25\%\) for resistive load without inductance. Class A stages are used in audio preamplifiers and low-power sensor interfaces where distortion is paramount.

8.3 Class B and Class AB Output Stage

The push-pull class B output stage uses a complementary pair: NMOS pulls the output high (sources current) and PMOS pulls it low (sinks current). Each transistor conducts for exactly half the cycle when the input swings the corresponding direction.

Crossover distortion occurs near zero crossing: both transistors are off for a dead zone of \(2V_T\) (or \(2V_{GS,th}\) for MOSFET). This severe nonlinearity limits class B to low-fidelity applications.

Class AB eliminates crossover distortion by providing a small quiescent current through both transistors. A floating battery (or two diode-connected transistors) of voltage \(V_{bias}\) keeps both transistors barely on at zero input:

\[ I_Q = \frac{1}{2}\mu_n C_{ox}\frac{W}{L}\left(\frac{V_{bias}}{2} - V_T\right)^2 \]

The quiescent current is typically 10–20% of the peak output current.

8.4 Short-Circuit Protection and Thermal Runaway

Output stages must be protected against short-circuit conditions (output accidentally connected to supply or ground). A current-sensing transistor monitors the output current via a small source-degeneration resistor and limits the drive to the output transistor when the current exceeds a threshold.

Thermal runaway is a concern in BJT-based class AB stages: increasing temperature increases \(I_C\), which further increases power dissipation and temperature in a positive feedback loop. MOSFET-based output stages have negative temperature coefficients (\(I_D\) decreases with \(T\) for \(V_{GS}\) above a crossover point), making them inherently more stable.

8.5 Output Stage in CMOS OTAs

CMOS OTAs intended for driving resistive loads (e.g., off-chip) often append a source-follower or class AB output stage to provide low output impedance while maintaining high gain in the core differential pair. The output stage introduces an additional pole that must be accounted for in the compensation design:

\[ \omega_{p,out} \approx \frac{g_{m,sf}}{C_{out}} \]

where \(C_{out}\) is the total capacitance at the output node.

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Chapter 9: Data Converters, Switched-Capacitor Circuits

9.1 Fundamentals of Data Conversion

9.1.1 Nyquist Criterion and Sampling

The Nyquist–Shannon theorem requires the sampling frequency \(f_s \geq 2 f_{max}\) to avoid aliasing, where \(f_{max}\) is the highest frequency in the signal. Aliasing causes high-frequency components to appear as low-frequency artifacts after sampling. Anti-aliasing filters (typically low-pass) must attenuate signals above \(f_s/2\) before the S/H.

9.1.2 Quantization Noise

An ideal \(N\)-bit ADC quantizes the analog input into \(2^N\) levels, each of width \(\Delta = V_{FS}/2^N\) (1 LSB). For a uniformly distributed input, the quantization error is uniform over \([-\Delta/2, +\Delta/2]\), giving an rms quantization noise of:

\[ e_{q,rms} = \frac{\Delta}{\sqrt{12}} = \frac{V_{FS}}{2^N\sqrt{12}} \]

For a full-scale sinusoidal input with amplitude \(V_{FS}/2\), the signal power is \((V_{FS}/2)^2/2 = V_{FS}^2/8\). The Signal-to-Quantization-Noise Ratio (SQNR) is:

\[ \text{SQNR} = \frac{V_{FS}^2/8}{V_{FS}^2/(12 \cdot 4^N)} = \frac{3}{2} \cdot 4^N = \frac{3}{2} \cdot 2^{2N} \]

In dB:

\[ \text{SQNR}_{dB} = 6.02N + 1.76 \text{ dB} \]

This is the fundamental limit: each additional bit of resolution adds 6.02 dB of SQNR.

9.1.3 Effective Number of Bits

In practice, non-idealities (thermal noise, distortion, mismatch) reduce the SQNR below the ideal. The Effective Number of Bits (ENOB) quantifies this:

\[ \text{ENOB} = \frac{\text{SNDR}_{dB} - 1.76}{6.02} \]

where SNDR is the Signal-to-Noise-and-Distortion Ratio measured with a near-full-scale sinusoidal input.

9.2 ADC Architectures

9.2.1 Flash ADC

A flash ADC uses \(2^N - 1\) comparators in parallel, each comparing the input to a different reference level spaced by 1 LSB. The comparator outputs form a thermometer code, which is decoded into a binary output.

Advantages: Single clock cycle conversion (inherently fast). Disadvantages: Exponential hardware growth (\(2^N - 1\) comparators, resistor ladder), power consumption, and input capacitance. Limited to \(N \leq 8\) bits in practice.

The dominant speed limitation is comparator metastability: if the differential input is smaller than the comparator’s noise floor or the input arrives near a decision boundary, the regenerative latch may not fully resolve within one clock period. The probability of metastability is:

\[ P_{meta} = \frac{\Delta V_{in}}{\Delta V_{sat}} \exp\!\left(-\frac{T_{clk} - T_{setup}}{\tau}\right) \]

where \(\tau = C_{latch}/g_{m,latch}\) is the regeneration time constant and \(T_{setup}\) accounts for digital logic delay. To minimize metastability, regeneration gain (and hence \(g_{m}/C\)) should be maximized.

9.2.2 Successive Approximation Register (SAR) ADC

The SAR ADC performs a binary search over \(N\) clock cycles. It consists of a comparator, an \(N\)-bit DAC, and a successive approximation register:

1. Set the MSB of the DAC output to 1, all others to 0: \(V_{DAC} = V_{FS}/2\).
2. Compare \(V_{in}\) to \(V_{DAC}\). If \(V_{in} > V_{DAC}\), keep the MSB = 1; otherwise set it to 0.
3. Set the next bit to 1 and repeat.

After \(N\) comparisons, the register holds the \(N\)-bit digital output.

Critical component: charge redistribution DAC. In CMOS SAR ADCs, the DAC is typically implemented as a binary-weighted capacitor array. Each capacitor \(C_k = 2^k C_{unit}\) switches between the input voltage (during sampling) and the reference voltage (during conversion). The DAC accuracy is limited by capacitor mismatch—random variations in \(C_k\) due to process—which introduces differential nonlinearity (DNL) and integral nonlinearity (INL). For an \(N\)-bit DAC with unit capacitor \(C_{unit}\), the required matching standard deviation is:

\[ \sigma_{C}/C \leq \frac{1}{2^{N-1}\sqrt{M}} \]

where \(M\) is the number of unit capacitors in the largest element (\(2^{N-1}\) for binary weighted). For 12-bit resolution, \(\sigma_C/C \leq 0.025\%\), achievable with careful layout (common-centroid, dummy capacitors).

Advantages: Low power, moderate speed, high resolution (\(N\) up to 16–18 bits), small area. Disadvantages: Conversion requires \(N\) clock cycles, so maximum input frequency without S/H is limited to \(f_s/(2\pi N)\).

9.2.3 Pipeline ADC

A pipeline ADC divides the conversion into \(K\) stages, each resolving \(b_k\) bits and passing a residue to the next stage. A typical 1.5-bit-per-stage pipeline:

1. Sample and hold: Capture the input.
2. Coarse quantization: A 1.5-bit sub-ADC (3 levels) determines a coarse code.
3. Residue generation: The DAC reconstructs the coarse approximation; the difference (residue) is amplified by 2 and passed to the next stage.
4. Digital correction: The 0.5-bit redundancy allows correction of comparator offsets up to \(\pm \Delta/4\).

The Multiplying DAC (MDAC) performs subtraction and multiplication in one operation using a switched-capacitor circuit:

\[ V_{residue} = 2V_{in} - V_{DAC,coarse} \]

The gain of 2 is realized by a switched-capacitor amplifier (charge redistribution). The accuracy of the gain-of-2 operation is critical: a gain error of \(\varepsilon\) in stage \(k\) causes an amplitude error that propagates through stages \(k+1\) to \(K\), contributing \(\varepsilon \cdot 2^{N-b_1-\cdots-b_k}\) to the output in LSBs.

9.2.4 Delta-Sigma (\(\Delta\Sigma\)) ADC

The \(\Delta\Sigma\) ADC uses oversampling and noise shaping to achieve high resolution without requiring tight component matching. Instead of a Nyquist-rate converter, it operates at an oversampling ratio (OSR) of \(M = f_s/(2f_{BW})\), then applies a digital decimation filter.

Oversampling gain: With white quantization noise spread over \([0, f_s/2]\), the in-band noise power after limiting to \([0, f_{BW}]\) is reduced by a factor of \(M\):

\[ e_{q,inband}^2 = \frac{\Delta^2}{12} \cdot \frac{2f_{BW}}{f_s} = \frac{\Delta^2}{12M} \]

This gives \(\frac{1}{2}\log_2 M\) extra bits per doubling of \(f_s\)—modest improvement of 0.5 bits per octave.

Noise shaping: The \(\Delta\Sigma\) modulator feeds back the quantization error through a loop filter \(H(z)\), shaping the noise power spectral density. For a first-order modulator with a single integrator:

\[ Y(z) = X(z) + (1 - z^{-1})E(z) \]

The signal transfer function (STF) is unity, and the noise transfer function (NTF) is:

\[ \text{NTF}(z) = 1 - z^{-1} \quad \Rightarrow \quad |\text{NTF}(e^{j\omega})|^2 = 4\sin^2(\omega/2) \]

This is a highpass function—it pushes quantization noise to higher frequencies, away from the signal band. The in-band noise power for a first-order modulator:

\[ e_{q,inband}^2 = \frac{\Delta^2}{12} \cdot \frac{\pi^2}{3M^3} \]

Resolution improvement: \(\frac{3}{2}\log_2 M + \frac{1}{2}\log_2(\pi^2/3) \approx 1.5\log_2 M - 0.3\) bits extra per doubling of OSR. The SQNR for a first-order \(\Delta\Sigma\):

\[ \text{SQNR}_{dB} \approx 6.02N + 1.76 + 30\log_{10}(M/\pi) - 5.17 \]

For an \(L\)th-order modulator (using \(L\) integrators in the loop filter), the NTF is \((1-z^{-1})^L\) and the SQNR improvement is \(\approx (2L+1) \cdot 9\) dB per doubling of OSR, providing \((L + 0.5)\) extra bits per octave.

Stability of \(\Delta\Sigma\) modulators: Higher-order modulators (\(L > 2\)) can become unstable if the input exceeds a fraction of the full scale. Stability conditions are analyzed using linear models (Lee’s criterion: keep \(|\text{NTF}|_\infty \leq 2\) for robust stability) or more rigorously through describing function analysis and simulation. Multi-bit quantizers in the loop increase the stable input range and reduce limit-cycle oscillations at the cost of DAC linearity requirements.

9.3 DAC Architectures

9.3.1 Binary-Weighted Resistor DAC

The simplest DAC uses binary-weighted resistors \(R, R/2, R/4, \ldots, R/2^{N-1}\) switched by digital bits. The output current is:

\[ I_{out} = \frac{V_{ref}}{R}\left(b_{N-1} + \frac{b_{N-2}}{2} + \cdots + \frac{b_0}{2^{N-1}}\right) \]

Resistor ratio errors (mismatch) limit accuracy; the MSB resistor’s ratio error directly adds an INL error of 1 LSB if the mismatch is \(2^{-(N+1)}\) of \(R\).

9.3.2 R-2R Ladder DAC

The R-2R ladder uses only two resistor values (R and 2R) regardless of resolution, making it much more practical to implement with good matching. The Thevenin equivalent at the output is:

\[ V_{out} = V_{ref} \cdot \frac{D}{2^N}, \quad D = \sum_{k=0}^{N-1} b_k 2^k \]

with Thevenin resistance \(R_{th} = R\). The R-2R ladder is widely used in audio DACs up to 16–18 bits.

9.3.3 Current-Steering DAC

High-speed DACs (100 MS/s to 1 GS/s) use current-steering architectures. Binary-weighted or unit-element (thermometer-coded) current sources switch current to the output. Thermometer coding avoids glitch energy associated with binary bit transitions (e.g., at midscale: all bits change from 0111…1 to 1000…0). The glitch energy is:

\[ E_{glitch} = \frac{1}{2}C_{parasitic}\Delta V^2 \]

For thermometer-coded current sources, only one current source switches per LSB step, minimizing glitch energy. The penalty is that \(2^N - 1\) current sources are needed, requiring careful common-centroid layout to minimize systematic gradient errors.

9.4 Switched-Capacitor Circuits

9.4.1 The Switched-Capacitor Resistor

A capacitor \(C\) switched at frequency \(f_{clk}\) between two nodes transfers charge \(q = C\Delta V\) per clock cycle. The equivalent resistance seen between the two nodes is:

\[ R_{eq} = \frac{1}{C f_{clk}} \]

This allows precise resistor values to be realized using only capacitors and switches (both well-controlled in CMOS), replacing the process-dependent and area-intensive diffusion resistors. The ratio \(C/f_{clk}\) sets the effective resistance; since both are well-controlled relative to each other, the accuracy of switched-capacitor circuits depends only on capacitor ratios, which can be matched to 0.01–0.1% using careful layout.

9.4.2 Switched-Capacitor Integrator

The parasitic-insensitive inverting SC integrator (due to Hosticka, Brodersen, and Gray, 1977) uses two phases \(\phi_1, \phi_2\):

• Phase \(\phi_1\): Input capacitor \(C_1\) samples \(V_{in}\). Integration capacitor \(C_2\) holds the previous output.
• Phase \(\phi_2\): \(C_1\) is discharged into \(C_2\) through the virtual ground of the OTA.

The discrete-time transfer function is:

\[ H(z) = -\frac{C_1}{C_2} \cdot \frac{z^{-1}}{1 - z^{-1}} \]

For frequencies well below \(f_{clk}/2\), this approximates a continuous-time integrator:

\[ H(j\omega) \approx -\frac{C_1}{C_2} \cdot \frac{f_{clk}}{j\omega} \]

with integrator frequency \(\omega_i = 2\pi f_{clk} C_1/C_2\). This frequency is set solely by the capacitor ratio and the clock frequency—both very well-controlled quantities.

9.4.3 Switched-Capacitor Filters

Complete filter transfer functions (lowpass, bandpass, notch) are realized by interconnecting SC integrators and summing nodes. The biquad section realizes a second-order transfer function:

\[ H(z) = \frac{a_0 + a_1 z^{-1} + a_2 z^{-2}}{1 + b_1 z^{-1} + b_2 z^{-2}} \]

The coefficients \(\{a_k, b_k\}\) are implemented as capacitor ratios. A complete \(N\)th-order filter is realized as a cascade (or ladder interconnection) of \(N/2\) biquad sections.

Advantages over continuous-time (Gm-C) filters:

• Accuracy set by capacitor ratios and clock frequency (both well-controlled)
• Insensitivity to process variations (no \(G_m\) trimming needed)
• Easy integration of complex poles with high \(Q\)

Limitations:

• Require aliasing of high-frequency noise (kT/C noise from switches) into the signal band
• Clock feedthrough introduces noise at harmonics of \(f_{clk}\)
• Limited to input signals well below \(f_{clk}/2\)

9.4.4 kT/C Noise

When a switch charges a capacitor \(C\), thermal noise in the switch resistance integrates onto the capacitor. The mean-square noise voltage on the capacitor is:

\[ \overline{v_n^2} = \frac{kT}{C} \]

independent of the switch resistance (a fundamental result of thermodynamics). For a 1 pF capacitor: \(\sqrt{kT/C} = \sqrt{4.14\times10^{-21}/10^{-12}} = 64\) µV rms. This sets a fundamental noise floor for switched-capacitor circuits; to achieve low noise (e.g., for a high-resolution ADC), larger capacitors must be used, at the cost of more area and power.

The input-referred noise of an SC amplifier with gain \(C_1/C_2 = G\) is:

\[ \overline{v_{n,in}^2} = \frac{kT}{C_1} + \frac{kT}{C_2 G^2} \]

For unity gain (G = 1, C_1 = C_2 = C): \(\overline{v_{n,in}^2} = 2kT/C\), as both sampling and integration operations each contribute kT/C noise.

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Appendix: Key Formulas Summary