These notes cover the full scope of ECE 240 at the University of Waterloo, following the topic sequence used in the Winter 2026 offering. The treatment is self-contained and derivation-heavy, integrating material from Sedra, Smith, Chan Carusone, and Gaudet, Microelectronic Circuits, 8th ed. (Oxford, 2020), and from Alexander and Sadiku, Fundamentals of Electric Circuits, 7th ed.

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Sources and References

The following public references form the primary bibliographic foundation for these notes:

• A. S. Sedra, K. C. Smith, T. Chan Carusone, and V. Gaudet, Microelectronic Circuits, 8th ed. New York: Oxford University Press, 2020. [Chapters 1–5, 7, 14, 16]
• C. K. Alexander and M. N. O. Sadiku, Fundamentals of Electric Circuits, 7th ed. New York: McGraw-Hill, 2020. [Chapters 2–8 for passive circuit analysis, first- and second-order circuits]
• B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed. New York: McGraw-Hill, 2016. [Chapters 3, 6, 9, 12 for small-signal models, current mirrors, frequency response, feedback]
• MIT OpenCourseWare 6.301 Solid State Circuits notes, available at ocw.mit.edu.
• R. C. Jaeger and T. N. Blalock, Microelectronic Circuit Design, 5th ed. New York: McGraw-Hill, 2015. [For supplementary treatment of BJT amplifiers and biasing]

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Chapter 1: Operational Amplifier Circuits

1.1 The Ideal Op-Amp Model

The operational amplifier — universally abbreviated op-amp — is a differential voltage amplifier with extremely high open-loop gain, extremely high input impedance, and essentially zero output impedance. For hand analysis we invoke the ideal op-amp model, which asserts three properties simultaneously:

1. Infinite open-loop voltage gain: \( A_{OL} \to \infty \).
2. Infinite input impedance: no current flows into either input terminal.
3. Zero output impedance: the output terminal is an ideal voltage source.

The virtual short is the workhorse of op-amp analysis. Combined with the zero-input-current condition, it reduces every ideal op-amp circuit to a problem in Kirchhoff’s current law (KCL) at a single node.

1.2 Inverting Amplifier

The canonical inverting configuration connects input \( v_s \) through resistor \( R_1 \) to the inverting terminal, with feedback resistor \( R_f \) from output \( v_o \) back to the same terminal, and the non-inverting terminal tied to ground.

Applying the virtual short: \( v_- = v_+ = 0 \). KCL at the inverting node (currents flowing into the node are positive):

\[ \frac{v_s - 0}{R_1} + \frac{v_o - 0}{R_f} = 0 \]

Solving directly:

\[ \frac{v_o}{v_s} = -\frac{R_f}{R_1} \]

The closed-loop gain is set entirely by the resistor ratio, independent of the open-loop gain — provided \( A_{OL} \) is large enough that the feedback loop is effective. The negative sign indicates a 180° phase inversion.

Input and output resistance. Because \( v_- \) is held at virtual ground by the feedback, the input resistance seen by \( v_s \) is simply \( R_1 \). The output resistance of the closed-loop amplifier is \( R_{out,CL} = R_{out,OL}/(1 + A_{OL} R_f / (R_1 + R_f)) \approx 0 \) for large \( A_{OL} \).

1.3 Non-Inverting Amplifier

Here \( v_s \) drives the non-inverting terminal directly, and the feedback network is a voltage divider from \( v_o \) to ground consisting of \( R_2 \) (to ground) and \( R_1 \) (to the inverting terminal).

Virtual short: \( v_- = v_+ = v_s \). The feedback voltage at the inverting terminal is:

\[ v_- = v_o \cdot \frac{R_2}{R_1 + R_2} \]

Setting this equal to \( v_s \):

\[ \frac{v_o}{v_s} = 1 + \frac{R_1}{R_2} \]

The gain is always \(\geq 1\) and the input resistance is theoretically infinite (the signal source drives the high-impedance non-inverting terminal directly).

1.4 Summing Amplifier and Difference Amplifier

Summing amplifier. Extend the inverting configuration to \( n \) inputs, each through its own resistor \( R_k \). KCL at the virtual-ground node gives:

\[ v_o = -R_f \left( \frac{v_1}{R_1} + \frac{v_2}{R_2} + \cdots + \frac{v_n}{R_n} \right) \]

Setting all \( R_k = R \) yields an equally-weighted inverting summer with gain \( -R_f / R \).

Difference amplifier. With four resistors \( R_1, R_2, R_3, R_4 \) in a bridge configuration, using superposition and the voltage-divider rule at the non-inverting terminal:

\[ v_o = \frac{R_4(R_1+R_2)}{R_1(R_3+R_4)}(v_2 - v_1) \]

when \( R_1/R_2 = R_3/R_4 \). This reduces to \( v_o = (R_2/R_1)(v_2 - v_1) \) in the matched case.

1.5 Integrator and Differentiator

Inverting integrator. Replace the feedback resistor \( R_f \) with a capacitor \( C \). In the \( s \)-domain:

\[ \frac{V_o(s)}{V_i(s)} = -\frac{1}{sRC} \]

In the time domain this becomes \( v_o(t) = -\frac{1}{RC}\int_0^t v_i(\tau)\,d\tau + v_o(0) \). The circuit is unstable at DC (the gain grows without bound at \( \omega = 0 \)), so practical integrators add a large resistor in parallel with \( C \) to limit the DC gain.

Differentiator. Swap the input resistor for a capacitor and keep the feedback resistor. The transfer function is:

\[ \frac{V_o(s)}{V_i(s)} = -sRC \]

Differentiators amplify high-frequency noise and are seldom used without a series resistor to limit high-frequency gain.

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Chapter 2: Frequency Response and Filters

2.1 First-Order RC and RL Circuits

A first-order system has a single energy-storage element and therefore a single pole. The transfer function takes the form

\[ H(s) = K \cdot \frac{s + z}{s + p} \]

for some zero \( z \) and pole \( p = 1/\tau \), where \( \tau \) is the time constant.

Low-pass RC filter. With input across the series combination and output taken across \( C \):

\[ H(j\omega) = \frac{1/j\omega C}{R + 1/j\omega C} = \frac{1}{1 + j\omega RC} \]

The magnitude is \( |H| = 1/\sqrt{1+(\omega/\omega_0)^2} \) where \( \omega_0 = 1/RC \) is the \(-3\,\text{dB}\) corner frequency. At \( \omega \gg \omega_0 \) the gain falls at \( -20\,\text{dB/decade}\).

High-pass RC filter. Output taken across \( R \):

\[ H(j\omega) = \frac{R}{R + 1/j\omega C} = \frac{j\omega RC}{1 + j\omega RC} = \frac{j\omega/\omega_0}{1 + j\omega/\omega_0} \]

This passes high frequencies and attenuates at \( -20\,\text{dB/decade}\) below \( \omega_0 \).

2.2 Second-Order RLC Circuits

A series RLC circuit driven by voltage \( V_s \) with output across \( C \) gives the prototype second-order low-pass transfer function:

\[ H(s) = \frac{\omega_0^2}{s^2 + 2\zeta\omega_0 s + \omega_0^2} \]

where the natural frequency \( \omega_0 = 1/\sqrt{LC} \) and the damping ratio \( \zeta = R/(2)\sqrt{C/L} \).

The poles are located at:

\[ s_{1,2} = -\zeta\omega_0 \pm \omega_0\sqrt{\zeta^2 - 1} \]

For \( \zeta < 1 \) (underdamped) the poles are complex conjugates: \( s_{1,2} = -\sigma \pm j\omega_d \) where the damped natural frequency is \( \omega_d = \omega_0\sqrt{1-\zeta^2} \).

Step response. Underdamped case (\( \zeta < 1 \)):

\[ v_C(t) = V_s\left[1 - e^{-\sigma t}\left(\cos\omega_d t + \frac{\sigma}{\omega_d}\sin\omega_d t\right)\right]u(t) \]

The output overshoots before settling. The percentage overshoot is \( \text{OS} = 100\exp(-\pi\zeta/\sqrt{1-\zeta^2}) \).

2.3 Frequency Response and Bode Plots

The Bode magnitude plot approximates \( |H(j\omega)| \) in dB using piecewise straight-line segments. For a transfer function written in standard form with corner frequencies \( \omega_{z_k} \) (zeros) and \( \omega_{p_k} \) (poles):

\[ |H(j\omega)|_{\text{dB}} = 20\log_{10}|K| + \sum_k 20\log_{10}\left|\frac{j\omega}{\omega_{z_k}}+1\right| - \sum_k 20\log_{10}\left|\frac{j\omega}{\omega_{p_k}}+1\right| \]

Each real pole contributes a slope change of \( -20\,\text{dB/decade}\) at its corner frequency; each real zero contributes \( +20\,\text{dB/decade}\). A second-order pole pair contributes \( -40\,\text{dB/decade}\) and a resonance peak of magnitude \( 1/(2\zeta) \) at \( \omega_0 \).

2.4 Active Filters with Op-Amps

Active filters exploit op-amp gain to realize filter functions with low-impedance sources and high-impedance loads, without inductors.

Sallen–Key low-pass filter (unity gain). A popular second-order topology using two RC networks and a unity-gain buffer:

\[ H(s) = \frac{\omega_0^2}{s^2 + (\omega_0/Q)s + \omega_0^2} \]

with \( \omega_0 = 1/\sqrt{R_1 R_2 C_1 C_2} \) and \( Q = \sqrt{R_1 R_2 C_1 C_2}/(C_2(R_1+R_2)) \). The designer chooses component values to realize the desired \( Q \) (Butterworth requires \( Q = 1/\sqrt{2} \approx 0.707 \)).

Cascading sections. Higher-order Butterworth and Chebyshev filters are realized by cascading first- and second-order op-amp sections, assigning each section a pole pair from the overall filter polynomial. The overall transfer function is the product of individual section functions.

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Chapter 3: Diode Physics, Models, and Basic Circuits

3.1 The p–n Junction Diode

A diode consists of a p-type semiconductor region in intimate contact with an n-type region. At equilibrium, diffusion of holes from p to n and electrons from n to p builds a depletion region depleted of mobile carriers, establishing a built-in potential \( V_0 \approx 0.6\,\text{V}\) to \(0.7\,\text{V}\) for silicon.

The ideal diode equation (Shockley equation) relates diode current \( i_D \) to voltage \( v_D \):

\[ i_D = I_S \left(e^{v_D / V_T} - 1\right) \]

where \( I_S \) is the reverse saturation current (typically \( 10^{-14}\,\text{A}\) to \( 10^{-12}\,\text{A}\) for silicon at room temperature) and \( V_T = kT/q \) is the thermal voltage. At \( T = 300\,\text{K}\), \( V_T \approx 25.9\,\text{mV} \).

For \( v_D \gg V_T \) (i.e., \( v_D \gtrsim 0.1\,\text{V} \) in practice), the \(-1\) term is negligible and the current rises exponentially with a slope of one decade per \( 2.3 V_T \approx 60\,\text{mV}\).

3.2 Diode Models

3.2.1 Ideal Diode Model

The simplest model treats the diode as a switch: it is a short circuit (zero voltage drop) when forward biased and an open circuit when reverse biased. This model suffices when circuit voltages are large compared to the 0.7 V forward drop.

3.2.2 Constant-Voltage-Drop (CVD) Model

A more realistic first-order model replaces the ideal diode with a series combination of an ideal diode and a fixed DC voltage source \( V_{D,on} \approx 0.7\,\text{V}\):

\[ v_D = V_{D,on} \quad \text{when } i_D > 0 \]

Analysis proceeds by assuming a diode state (on or off), computing the resulting currents and voltages using the model, and then verifying that the assumed state is consistent.

3.2.3 Piecewise-Linear (PWL) Model

The PWL model adds a forward resistance \( r_d \) representing the slope of the \( i_D\text{–}v_D \) characteristic in the forward-bias region:

\[ v_D = V_{D0} + r_d \cdot i_D \quad \text{for } i_D > 0 \]

Here \( V_{D0} \) is the threshold voltage (intercept of the linearized characteristic) and \( r_d \) is the inverse slope. Typical silicon values: \( V_{D0} \approx 0.65\,\text{V}\), \( r_d \approx 2\,\Omega\) to \( 20\,\Omega \) depending on the current level.

3.2.4 Small-Signal Model

When the diode operates with a DC bias current \( I_D \) and a small superimposed AC signal \( v_d \ll V_T \), we linearize the Shockley equation around the operating point:

\[ i_D \approx I_D + \frac{dI_D}{dV_D}\bigg|_{Q} v_d = I_D + g_d v_d \]

The small-signal conductance is:

\[ g_d = \frac{I_S}{V_T} e^{V_D/V_T} = \frac{I_D + I_S}{V_T} \approx \frac{I_D}{V_T} \]

The small-signal resistance (dynamic resistance) is:

\[ r_d = \frac{1}{g_d} = \frac{V_T}{I_D} \]

At \( I_D = 1\,\text{mA}\), \( r_d \approx 25.9\,\Omega \). The small-signal equivalent circuit is simply a resistor \( r_d \).

3.3 Load-Line Analysis

For a nonlinear element (diode) in series with a linear Thévenin source, the operating point (Q-point) lies at the intersection of the device characteristic curve with the load line. The load line for source \( V_{DD} \) and series resistance \( R \) is:

\[ i_D = \frac{V_{DD} - v_D}{R} \]

This is a straight line with \( y\)-intercept \( V_{DD}/R \) and \( x\)-intercept \( V_{DD} \). The Q-point \( (V_{DQ}, I_{DQ}) \) satisfies both this equation and the Shockley equation simultaneously.

3.4 Rectifier Circuits

3.4.1 Half-Wave Rectifier

A single diode in series with a load resistor. On positive half-cycles the diode conducts; on negative half-cycles it blocks. Using the CVD model with \( V_{D,on} = 0.7\,\text{V}\):

\[ v_o = \begin{cases} v_s - 0.7 & v_s > 0.7\,\text{V} \\ 0 & v_s \leq 0.7\,\text{V} \end{cases} \]

The DC (average) output for a sinusoidal input \( V_m \sin\omega t \) is:

\[ V_{DC} = \frac{V_m - 0.7}{\pi} \]

Ripple and filter capacitor. Adding a capacitor \( C \) in parallel with the load \( R_L \) smooths the output. Between conduction pulses the capacitor discharges through \( R_L \) with time constant \( R_L C \). The peak-to-peak ripple voltage is approximately:

\[ V_r \approx \frac{V_m}{f R_L C} \]

where \( f \) is the supply frequency. For small ripple, the conduction angle is short and the peak diode current is large: \( i_{D,peak} \approx C\,dv/dt|_{peak} \).

3.4.2 Full-Wave Bridge Rectifier

Four diodes in a bridge configuration. On positive half-cycles diodes \( D_1 \) and \( D_3 \) conduct; on negative half-cycles \( D_2 \) and \( D_4 \) conduct. Two diode drops reduce the output:

\[ v_o = |v_s| - 2 \times 0.7 = |v_s| - 1.4\,\text{V} \]

The DC output is:

\[ V_{DC} = \frac{2(V_m - 1.4)}{\pi} \]

and the ripple frequency is \( 2f \), so for the same \( R_L C \) the ripple is halved compared to the half-wave circuit.

3.5 Clippers and Clampers

Clippers limit the output waveform to a specified range. A series clipper with a DC bias \( V_B \) clips the output at \( V_B + 0.7\,\text{V}\). A parallel clipper places the diode in shunt: when \( v_s > V_K \), the diode conducts, clamping the output to \( V_K \).

Clampers (DC restorers) shift the entire AC waveform up or down so that a specified peak coincides with a reference. A capacitor in series with the signal, together with a diode to ground, clamps the negative peaks to 0 V (or \( V_B \) if a battery is added). The capacitor charges to the peak value and then acts as a DC offset source.

3.6 Zener Diode Voltage Regulator

A Zener diode is designed to operate in reverse breakdown. In the breakdown region the current can vary over a wide range with only a small change in voltage, which is the regulated output voltage \( V_Z \).

The small-signal Zener model consists of a DC voltage source \( V_{Z0} \) (the knee voltage) in series with a small incremental resistance \( r_z\):

\[ v_Z = V_{Z0} + r_z \cdot i_Z \quad \text{(in breakdown, } i_Z > 0 \text{ defined as reverse current)} \]

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Chapter 4: MOSFET Physics, Models, and Biasing

4.1 MOSFET Structure and Operation

The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is the dominant active device in modern integrated circuits. An n-channel MOSFET (NMOS) consists of a p-type silicon substrate with two heavily doped n\(^+\) regions (source and drain) separated by a channel region. A thin gate oxide (SiO\(_2\)) and a metal (or polysilicon) gate electrode sit above the channel.

Threshold voltage \( V_{tn} \). When the gate-to-source voltage \( v_{GS} \) exceeds the threshold voltage \( V_{tn} \), an inversion layer of electrons forms at the semiconductor surface beneath the gate oxide, connecting source to drain. Below threshold the channel is absent (or weakly present in subthreshold conduction).

Physical origins of \( V_{tn} \). The threshold voltage depends on the oxide capacitance \( C_{ox} = \varepsilon_{ox}/t_{ox} \), the body doping concentration, the flat-band voltage (related to work function differences and fixed oxide charges), and any applied body–source voltage \( v_{BS} \). The body effect increases \( V_{tn} \) when \( v_{BS} < 0 \).

4.2 MOSFET Large-Signal (DC) Current–Voltage Characteristics

4.2.1 Triode (Linear) Region

When \( v_{GS} > V_{tn} \) and \( v_{DS} < v_{GS} - V_{tn} \equiv V_{GS,ov} \) (the overdrive voltage), the channel exists from source to drain and the current is:

\[ i_D = k_n \left[ (v_{GS} - V_{tn})v_{DS} - \frac{v_{DS}^2}{2} \right], \quad k_n = \mu_n C_{ox} \frac{W}{L} \]

where \( \mu_n \) is the electron mobility, \( W \) the channel width, and \( L \) the channel length. The process transconductance parameter \( k_n' = \mu_n C_{ox} \) is a technology constant.

For small \( v_{DS} \) (deep triode), the quadratic term is negligible and the device behaves as a resistor:

\[ i_D \approx k_n (v_{GS} - V_{tn}) v_{DS} \implies r_{DS} = \frac{1}{k_n(v_{GS}-V_{tn})} \]

4.2.2 Saturation Region

When \( v_{DS} \geq v_{GS} - V_{tn} \), the channel pinches off at the drain end. The current saturates and (in the ideal long-channel model) becomes independent of \( v_{DS} \):

\[ i_D = \frac{k_n}{2}(v_{GS} - V_{tn})^2 = \frac{k_n}{2}V_{GS,ov}^2 \]

4.2.3 PMOS Transistor

A PMOS transistor uses a p-channel in an n-type substrate. It operates with \( v_{SG} > |V_{tp}| \) (source is the terminal at higher potential), and the drain current flows from source to drain (conventional positive current into the drain for NMOS; out of drain for PMOS). The equations are symmetric with all voltages referenced to the source and \( k_p = \mu_p C_{ox}(W/L) \).

4.3 MOSFET Biasing (DC Operating Point)

The purpose of biasing is to establish a stable Q-point \( (V_{GSQ}, V_{DSQ}, I_{DQ}) \) in the saturation region so that small-signal amplification is possible. The Q-point must remain in saturation for all expected signal swings: \( V_{DSQ} > V_{GSQ} - V_{tn} \).

4.3.1 Fixed-Bias and Self-Bias Circuits

In the simplest single-supply bias, \( V_{GS} \) is set by a voltage divider from \( V_{DD} \). More robustly, a source resistor \( R_S \) provides negative feedback: if \( I_D \) increases, \( V_S = I_D R_S \) rises, reducing \( V_{GS} = V_G - V_S \) and thereby reducing \( I_D \).

The standard four-element bias network uses \( R_{G1} \), \( R_{G2} \), \( R_D \), and \( R_S \):

\[ V_G = V_{DD} \cdot \frac{R_{G2}}{R_{G1}+R_{G2}}, \quad V_{GS} = V_G - I_D R_S \]

Substituting into \( I_D = (k_n/2)(V_{GS}-V_{tn})^2 \) yields a quadratic in \( I_D \). The physically meaningful root (positive, with \( V_{GS} > V_{tn} \)) gives the Q-point.

4.3.2 Load-Line Analysis for MOSFETs

The DC load line for a drain circuit with supply \( V_{DD} \) and drain resistor \( R_D \) is:

\[ V_{DS} = V_{DD} - I_D R_D \]

This straight line on the \( i_D\text{–}v_{DS} \) plane intersects the device characteristic at the Q-point. The designer chooses \( R_D \) (and bias voltages) so the Q-point sits in saturation with sufficient headroom for signal swing.

4.4 Small-Signal Model of the MOSFET

Linearizing the large-signal equations around the Q-point yields the small-signal (or incremental) model. There are two equivalent forms.

Transconductance \( g_m \). The primary parameter:

\[ g_m = \frac{\partial i_D}{\partial v_{GS}}\bigg|_Q = k_n(V_{GS}-V_{tn}) = k_n V_{GS,ov} = \sqrt{2k_n I_{DQ}} \]

All three expressions are equivalent; the last is useful when only \( I_{DQ} \) is known.

Output resistance \( r_o \). Due to channel-length modulation:

\[ r_o = \frac{1}{\lambda I_{DQ}} \]

The small-signal equivalent circuit (valid for frequencies well below the transition frequency) contains:

• A voltage-controlled current source \( g_m v_{gs} \) from drain to source.
• Output resistance \( r_o \) from drain to source.
• No current into the gate (at low frequency).

At higher frequencies, gate capacitances \( C_{gs} \) and \( C_{gd} \) are added.

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Chapter 5: MOSFET Amplifier Configurations

5.1 Small-Signal Analysis Methodology

To analyze any MOSFET amplifier:

1. Find the DC Q-point by setting all AC sources to zero.
2. Draw the small-signal equivalent circuit: replace the MOSFET with its \( g_m \) source and \( r_o \), short all DC supplies, replace large coupling and bypass capacitors with short circuits (midband analysis).
3. Apply circuit analysis (KVL, KCL, node voltages) to find the desired gains and impedances.

5.2 Common-Source Amplifier

The input signal drives the gate; the output is taken from the drain; the source is at AC ground (either directly or via a large bypass capacitor across \( R_S \)).

Voltage gain. The drain current signal is \( i_d = g_m v_{gs} = g_m v_i \). With \( R_D \) and \( r_o \) in parallel as the effective drain resistance \( R_D' = R_D \| r_o \):

\[ v_o = -i_d(R_D\|r_o\|R_L) = -g_m v_i (R_D\|r_o\|R_L) \]\[ A_v = \frac{v_o}{v_i} = -g_m(R_D\|r_o\|R_L) \]

The negative sign indicates signal inversion. Neglecting \( r_o \) (a common approximation when \( r_o \gg R_D \)):

\[ A_v \approx -g_m R_D \]

Input and output resistance. The input resistance seen at the gate is infinite in the ideal model (the gate draws no DC current). In practice, the bias resistors appear in parallel: \( R_{in} = R_{G1}\|R_{G2} \). The output resistance looking into the drain (with input source zeroed) is \( R_{out} = R_D \| r_o \approx R_D \).

5.3 Common-Source Amplifier with Source Resistance

When the source resistor \( R_S \) is not fully bypassed, the signal voltage at the source is \( v_s = i_d R_S \), reducing the effective \( v_{gs} \):

\[ v_{gs} = v_i - v_s = v_i - g_m v_{gs} R_S \implies v_{gs} = \frac{v_i}{1 + g_m R_S} \]

The gain becomes:

\[ A_v = \frac{-g_m R_D}{1 + g_m R_S} \]

This is the source-degenerated CS amplifier. The gain is reduced but the input–output linearity and bandwidth are improved (series feedback).

5.4 Common-Gate Amplifier

The gate is at AC ground; the input drives the source; the output is at the drain. This topology is non-inverting.

Voltage gain. The drain current signal \( i_d = g_m v_{gs} = -g_m v_i \) (note \( v_{gs} = -v_i \) since the gate is grounded and \( v_s = v_i \)):

\[ A_v = \frac{v_o}{v_i} = g_m(R_D\|r_o\|R_L) \approx g_m R_D \]

The gain is positive (non-inverting) and the same magnitude as the common-source. The key distinction is the input resistance: looking into the source terminal,

\[ R_{in} = \frac{1}{g_m} \| r_o \approx \frac{1}{g_m} \]

which is low (typically tens of ohms). This makes the CG amplifier suitable for current-mode inputs or as a cascode stage following a CS stage to extend bandwidth.

5.5 Common-Drain Amplifier (Source Follower)

The drain is at AC ground (connected directly to \( V_{DD} \)); the input is at the gate; the output is taken from the source.

Voltage gain. With output resistance \( R_S \| r_o \) and \( v_{gs} = v_i - v_o \):

\[ v_o = g_m v_{gs}(R_S\|r_o) = g_m(v_i - v_o)(R_S\|r_o) \]

Solving:

\[ A_v = \frac{v_o}{v_i} = \frac{g_m(R_S\|r_o)}{1 + g_m(R_S\|r_o)} < 1 \]

The gain is always less than unity but approaches 1 when \( g_m R_S \gg 1 \). The source follower is used as a buffer: it has high input resistance (same as CS) and low output resistance:

\[ R_{out} = \frac{1}{g_m} \| R_S \| r_o \approx \frac{1}{g_m} \]

5.6 Comparison of MOSFET Configurations

Parameter	Common-Source	Common-Gate	Common-Drain
Voltage gain	\(-g_m R_D\)	\(+g_m R_D\)	\(\approx 1\)
Input resistance	High (\( R_{G1}\|R_{G2} \))	Low (\( 1/g_m \))	High (\( R_{G1}\|R_{G2} \))
Output resistance	\( R_D \| r_o \)	\( R_D \| r_o \)	\( 1/g_m \)
Phase shift	180°	0°	0°

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Chapter 6: Frequency Response of MOSFET Amplifiers

6.1 MOSFET High-Frequency Model

At high frequencies, the parasitic capacitances of the MOSFET become significant:

• \( C_{gs} \): gate-to-source capacitance (primarily from the gate-channel overlap and inversion layer). Typical: \( C_{gs} \approx (2/3)C_{ox}WL + C_{ov}W \).
• \( C_{gd} \): gate-to-drain overlap capacitance (much smaller, but bridging input and output). \( C_{gd} \approx C_{ov}W \).
• \( C_{db}, C_{sb} \): drain-body and source-body junction capacitances.

6.2 Miller Effect

The Miller effect is the apparent multiplication of a bridging (feedback) capacitance seen at the input. For a CS amplifier with gain \( A_v = -g_m R_D \), the gate-to-drain capacitance \( C_{gd} \) appears at the input as:

\[ C_{M} = C_{gd}(1 - A_v) = C_{gd}(1 + g_m R_D) \]

This can be a factor of 10 to 100 larger than \( C_{gd} \) itself, dramatically reducing the bandwidth of the CS stage. At the output:

\[ C_{M,out} = C_{gd}\left(1 - \frac{1}{A_v}\right) \approx C_{gd} \]

6.3 Short-Circuit Time Constants Method

The short-circuit time constant (SCTC) method estimates the upper \(-3\,\text{dB}\) frequency without finding the full transfer function. For each capacitor \( C_k \) in the circuit, the resistance \( R_k \) seen by that capacitor is computed with all other capacitors replaced by short circuits and all independent sources set to zero. The upper cutoff is:

\[ \omega_H \approx \frac{1}{\sum_k R_k C_k} \]

Application to CS amplifier. With source resistance \( R_{sig} \), drain resistance \( R_D \), and load \( R_L \):

\[ R_{gs} = R_{sig}\|(\infty) = R_{sig} \]\[ R_{gd} = R_{sig} + (R_D\|R_L) + g_m R_{sig}(R_D\|R_L) \]

The dominant pole is often set by \( C_{gd} R_{gd} \) due to the Miller multiplication, even though \( C_{gd} \ll C_{gs} \).

6.4 Transition Frequency \( f_T \)

The transition frequency (unity-gain bandwidth) \( f_T \) is defined as the frequency at which the short-circuit current gain \( h_{fe} \) of the device (or equivalently the magnitude of the current gain from gate to drain) falls to unity. For the MOSFET:

\[ f_T = \frac{g_m}{2\pi(C_{gs} + C_{gd})} \approx \frac{g_m}{2\pi C_{gs}} = \frac{\mu_n V_{GS,ov}}{2\pi L^2} \]

This is a figure of merit for the transistor’s intrinsic speed. Shorter channel length \( L \) directly increases \( f_T \), which is why channel scaling drives performance improvements.

6.5 Open-Circuit Time Constants for Low-Frequency Poles

Coupling and bypass capacitors create low-frequency poles. The open-circuit time constant (OCTC) method estimates the lower \(-3\,\text{dB}\) frequency: for each capacitor \( C_k \), compute the resistance \( R_k^0 \) with all other capacitors open-circuited:

\[ \omega_L \approx \sum_k \frac{1}{R_k^0 C_k} \]

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Chapter 7: CMOS Digital Logic Circuits

7.1 CMOS Inverter

The complementary MOSFET (CMOS) inverter consists of a PMOS transistor (pull-up) and an NMOS transistor (pull-down) with gates tied together at the input and drains tied together at the output.

Operation. When \( v_I = V_{DD} \): NMOS is on (\( v_{GS,N} = V_{DD} > V_{tn} \)), PMOS is off (\( v_{SG,P} = 0 < |V_{tp}| \)), so \( v_O \approx 0\,\text{V}\). When \( v_I = 0 \): NMOS is off, PMOS is on, \( v_O \approx V_{DD} \). The inverter produces a logic complement.

Static power dissipation. In steady state, only one transistor conducts at a time (in the ideal switch model) and no DC current flows, giving zero static power dissipation — the great advantage of CMOS over earlier NMOS-only logic families.

Switching threshold \( V_M \). The DC transfer characteristic has a steep transition region around the switching threshold \( V_M \approx V_{DD}/2 \) (for matched devices). To find \( V_M \) precisely, set \( v_I = v_O = V_M \) and note that both devices are in saturation at this point:

\[ k_n(V_M - V_{tn})^2 = k_p(V_{DD} - V_M - |V_{tp}|)^2 \]

Solving:

\[ V_M = \frac{V_{tn} + \sqrt{k_p/k_n}(V_{DD}-|V_{tp}|)}{1 + \sqrt{k_p/k_n}} \]

For \( k_n = k_p \) and \( V_{tn} = |V_{tp}| \), \( V_M = V_{DD}/2 \).

7.2 Noise Margins

The noise margin quantifies how much noise the logic level can tolerate before a logic error occurs. From the DC transfer characteristic, \( V_{IL} \) (maximum input low) and \( V_{IH} \) (minimum input high) are defined as the points where the slope \( dv_O/dv_I = -1 \):

\[ NM_L = V_{IL} - V_{OL}, \quad NM_H = V_{OH} - V_{IH} \]

For a well-designed CMOS inverter, \( V_{OL} \approx 0 \), \( V_{OH} \approx V_{DD} \), and the noise margins are large.

7.3 Dynamic (Switching) Power

Dynamic power arises from charging and discharging the load capacitance \( C_L \) (sum of drain capacitances, wiring, and next-stage gate capacitances). Each output transition from low to high charges \( C_L \) to \( V_{DD} \); the energy stored is \( \frac{1}{2}C_L V_{DD}^2 \). Each transition from high to low discharges the capacitor, dissipating the stored energy as heat in the NMOS. Both transitions together dissipate \( C_L V_{DD}^2 \) per clock cycle:

\[ P_{dyn} = \alpha C_L V_{DD}^2 f \]

where \( \alpha \) is the activity factor (probability of a transition per clock cycle, \( 0 \leq \alpha \leq 1 \)) and \( f \) is the clock frequency. Voltage scaling (reducing \( V_{DD} \)) is therefore the most effective way to reduce dynamic power — it appears quadratically.

7.4 NAND and NOR Gates

CMOS NAND. Two NMOS in series (pull-down) and two PMOS in parallel (pull-up). The output is low only when both inputs are high (both NMOS on, both PMOS off). Sizing: for equal pull-down and pull-up strengths, series NMOS must be twice as wide as the inverter NMOS (since two are in series), while parallel PMOS can be the same size.

CMOS NOR. Two NMOS in parallel (pull-down) and two PMOS in series (pull-up). The output is high only when both inputs are low. Series PMOS must be twice as wide as the inverter PMOS.

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Chapter 8: Operational Amplifier Internals and Frequency Compensation

8.1 Internal Structure of a CMOS Op-Amp

A typical two-stage CMOS op-amp consists of:

1. First stage (differential pair with current mirror load): Provides the differential gain and common-mode rejection.
2. Second stage (common-source with active load): Provides additional gain.
3. Output stage (optional source follower): Provides low output impedance.

Differential pair. Two matched MOSFETs \( M_1 \) and \( M_2 \) share a tail current source \( I_{SS} \). The differential transconductance of the pair is \( G_m = g_{m1} = g_{m2} \). The differential voltage gain of the first stage is:

\[ A_{v1} = -G_m(r_{o2}\|r_{o4}) \]

where \( r_{o2} \) and \( r_{o4} \) are the output resistances of the signal and load transistors respectively.

8.2 Differential Gain and Common-Mode Rejection

Differential gain \( A_d \). The output voltage responds to the difference \( v_{id} = v_+ - v_- \):

\[ v_o = A_d \cdot v_{id} \]

Common-mode gain \( A_{cm} \). The output also responds (to a lesser degree) to the common-mode input \( v_{ic} = (v_+ + v_-)/2 \):

\[ v_o = A_{cm} \cdot v_{ic} \]

Common-Mode Rejection Ratio (CMRR):

\[ \text{CMRR} = \left|\frac{A_d}{A_{cm}}\right| \]

expressed in dB as \( 20\log_{10}(\text{CMRR}) \). For an ideal differential pair with perfect tail current source, \( A_{cm} = 0 \) and CMRR is infinite. In practice, mismatches and finite tail-source impedance \( R_{SS} \) limit the CMRR:

\[ A_{cm} \approx \frac{-\Delta R_D/2}{R_{SS} + \Delta R_D/2} \]

for small mismatch \( \Delta R_D \) in the drain resistors.

8.3 Current Mirrors

Current mirrors are the workhorses of analog IC design, used to bias the differential pair and as active loads.

Basic MOSFET current mirror. A reference transistor \( M_{ref} \) has its gate and drain tied together (diode-connected), forcing it into saturation with current \( I_{ref} \). The gate voltage is connected to the gate of a second transistor \( M_{out} \), which mirrors the current:

\[ I_{out} = I_{ref} \cdot \frac{(W/L)_{out}}{(W/L)_{ref}} \]

assuming both devices have the same \( V_{GS} \) (same gate–source bias). The ratio of W/L ratios sets the current scaling.

Output resistance. Due to channel-length modulation, the output current depends slightly on the output voltage:

\[ I_{out}(v_o) = I_{ref}\left(1 + \lambda (v_o - V_{GS,ref})\right) \]

The incremental output resistance is \( r_{out} = r_{o,out} \). A cascode current mirror greatly increases this by adding a cascode transistor, achieving \( r_{out} \approx g_m r_o^2 \gg r_o \).

8.4 Frequency Compensation and the Dominant-Pole Technique

An op-amp used in a feedback loop can become unstable if the phase shift at the unity-gain frequency exceeds 180°. Compensation ensures adequate phase margin.

Dominant-pole compensation. A compensation capacitor \( C_c \) is added (often between the output of the first stage and the input of the second stage). By Miller effect, \( C_c \) appears at the first-stage output as \( C_c(1 + A_{v2}) \), creating a very low dominant pole:

\[ \omega_{p1} \approx \frac{1}{R_1 C_c (1+|A_{v2}|)} \approx \frac{1}{R_1 C_c |A_{v2}|} \]

This pulls the open-loop gain to zero dB before the second pole \( \omega_{p2} \) causes significant additional phase shift. The unity-gain bandwidth (gain-bandwidth product) is:

\[ \omega_u = A_0 \cdot \omega_{p1} = \frac{G_m}{C_c} \]

Phase margin. For stability with negative feedback, the phase of the loop gain \( T(j\omega) \) should not reach \(-180°\) at the frequency where \( |T| = 1 \). A phase margin of 45° to 60° is typically required. To ensure this, the unity-gain frequency is set well below the second pole:

\[ \omega_u < \omega_{p2} \implies G_m/C_c < g_{m6}/C_L \]

(for a two-stage op-amp with second stage transconductance \( g_{m6} \) and load capacitance \( C_L \)).

Right-half-plane zero. The feed-forward path through \( C_c \) creates a right-half-plane (RHP) zero at \( \omega_z = g_{m6}/C_c \), which adds positive phase shift at the wrong sign — it worsens phase margin. A nulling resistor in series with \( C_c \) can push this zero to infinity or move it to the left half-plane.

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Chapter 9: Feedback Theory

9.1 The General Feedback Topology

A feedback amplifier consists of a forward amplifier with gain \( A \) and a feedback network with feedback factor \( \beta_f \). The closed-loop gain is:

\[ A_f = \frac{A}{1 + A\beta_f} \]

The quantity \( T = A\beta_f \) is the loop gain. For \( T \gg 1 \):

\[ A_f \approx \frac{1}{\beta_f} \]

The closed-loop gain is determined almost entirely by the feedback network, which is typically a passive resistor network and therefore stable and precise.

9.2 The Four Feedback Topologies

Feedback is classified by how the feedback signal is sampled (at the output) and mixed (at the input). This gives four topologies:

Topology	Output Sampling	Input Mixing	Gain Type	Effect on Impedances
Series–series	Current	Voltage (series)	Transresistance	\(R_{in} \uparrow\), \(R_{out} \uparrow\)
Series–shunt	Voltage	Voltage (series)	Voltage gain	\(R_{in} \uparrow\), \(R_{out} \downarrow\)
Shunt–series	Current	Current (shunt)	Current gain	\(R_{in} \downarrow\), \(R_{out} \uparrow\)
Shunt–shunt	Voltage	Current (shunt)	Transconductance	\(R_{in} \downarrow\), \(R_{out} \downarrow\)

The most common configuration for voltage amplifiers is series–shunt (voltage sampling, series mixing), which increases input resistance and decreases output resistance — ideal buffer behavior.

9.3 Determining \( A \) and \( \beta_f \) Using the Two-Port Method

To apply the feedback formulae, the amplifier and feedback networks must be properly separated. The standard method (Sedra/Smith two-port approach):

1. Break the loop at a convenient point.
2. Replace the feedback network with its loading on the amplifier side (set the controlled source in the feedback network to zero; retain the passive loading).
3. Compute the open-loop gain \( A \) of the loaded amplifier.
4. Compute \( \beta_f \) as the ratio of the feedback signal to the output signal (with the amplifier input zeroed).

This procedure correctly accounts for loading at both input and output ports.

9.4 Stability and the Nyquist Criterion

A feedback system is stable if the closed-loop poles are in the left half of the \( s \)-plane. The Nyquist criterion assesses stability from the open-loop frequency response: if the Nyquist plot of \( T(j\omega) = A(j\omega)\beta_f \) does not encircle the \(-1\) point, the closed-loop system is stable.

Bode stability criterion (for minimum-phase systems). The system is stable if, at the frequency where \( |T(j\omega)| = 1 \) (the gain crossover frequency \( \omega_c \)), the phase of \( T \) is greater than \( -180° \). The phase margin is:

\[ PM = 180° + \angle T(j\omega_c) \]

A phase margin of 45° or more ensures that the closed-loop step response shows acceptable transient behavior (overshoot less than about 20%).

Gain margin. At the phase crossover frequency \( \omega_\phi \) where \( \angle T = -180° \), the gain margin is:

\[ GM = -20\log_{10}|T(j\omega_\phi)|\,\text{dB} \]

A gain margin of at least 6 dB is typically required.

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Chapter 10: Active Filter Design and Signal Conditioning

10.1 Filter Specifications and Approximations

A filter is specified by its passband ripple, stopband attenuation, and transition band. Common approximations:

Butterworth (maximally flat). All poles on a circle of radius \( \omega_0 \) in the \( s \)-plane. The magnitude response is:

\[ |H(j\omega)|^2 = \frac{1}{1+(\omega/\omega_0)^{2n}} \]

with \( n \) poles. The response is monotone in both bands; no equiripple.

Chebyshev Type I. Equiripple in the passband, monotone in the stopband. Achieves steeper rolloff than Butterworth for the same order, at the cost of passband ripple.

Bessel–Thomson. Maximally flat group delay (approximately linear phase) in the passband; poor selectivity. Used when preserving pulse shape is important.

10.2 Cascaded Biquad Sections

High-order filters are realized as a cascade of second-order (biquadratic) sections. Each biquad implements one complex conjugate pole pair. The transfer function of a second-order low-pass section is:

\[ H(s) = \frac{K\omega_0^2}{s^2 + (\omega_0/Q)s + \omega_0^2} \]

The Tow–Thomas (state-variable) biquad uses three op-amps (two integrators and a summer) to realize any second-order function with independently tunable \( \omega_0 \) and \( Q \). It is widely used in precision filter design due to its low sensitivity to component variations.

10.3 Instrumentation Amplifier

The instrumentation amplifier (INA) amplifies the difference between two signals with high input impedance, high CMRR, and gain set by a single resistor. It consists of two non-inverting buffers followed by a difference amplifier:

\[ v_o = \left(1 + \frac{2R_1}{R_G}\right)\frac{R_f}{R_f'}(v_2 - v_1) \]

The gain is set by \( R_G \); the CMRR is determined by the resistor matching in the difference amplifier stage.

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Chapter 11: Practical Considerations and Laboratory Techniques

11.1 Real Op-Amp Non-Idealities

Input offset voltage \( V_{OS} \). Due to mismatches in the differential pair, a small voltage must be applied between the input terminals to force the output to zero. Typical: \( |V_{OS}| < 5\,\text{mV} \) for general-purpose, \( < 25\,\mu\text{V} \) for precision op-amps. In an inverting amplifier with gain \( A \), the offset is amplified to \( A \cdot V_{OS} \) at the output.

Input bias current \( I_B \). The average DC current into the two input terminals. In BJT op-amps this can be 50 nA to 1 µA; in CMOS op-amps it is typically \(< 1\,\text{pA}\). Bias current flowing through feedback resistors creates an output offset voltage \( \approx I_B R_f \).

Input offset current \( I_{OS} \). The difference between the two input bias currents. Placing equal resistances at both input terminals to ground cancels the common-mode bias current term, leaving only the offset current contribution \( I_{OS} R_f \).

Slew rate. The maximum rate of change of the output voltage, limited by the finite charging current available to drive internal capacitances:

\[ SR = \frac{I_{max}}{C_{comp}} \]

For a sinusoidal output of amplitude \( V_m \) and frequency \( f \), the required slew rate is \( 2\pi f V_m \). If the applied slew rate exceeds \( SR \), the output is distorted (slews linearly rather than sinusoidally).

Gain-bandwidth product (GBP). The open-loop gain \( A_{OL}(f) \) falls at 20 dB/decade above the dominant pole frequency \( f_{p1} \). The GBP = \( A_0 f_{p1} \) is constant. For a closed-loop gain of \( |A_v| \), the bandwidth is approximately \( f_{BW} = \text{GBP}/|A_v| \).

11.2 Measurement and Debugging

DC measurements. Use a high-impedance digital multimeter. Probe directly at device terminals; avoid long leads that add inductance.

AC measurements. An oscilloscope reveals waveform shape, amplitude, and phase. When measuring amplifier frequency response, use the signal generator’s internal 50 Ω output impedance as part of the source resistance, or explicitly account for it in calculations.

Decoupling capacitors. Every power supply rail should have a 100 nF ceramic capacitor placed as close as possible to the supply pin of each IC, plus a larger (10 µF) electrolytic capacitor at the board power entry. Parasitic inductance in the supply traces combined with rapid current demands creates supply noise that degrades op-amp performance.

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Chapter 12: Synthesis — Putting It All Together

12.1 Signal Path Design

A complete signal-conditioning chain typically consists of:

1. Sensor producing a small, often noisy differential signal.
2. Instrumentation amplifier providing high CMRR differential gain.
3. Active low-pass filter removing aliasing and high-frequency noise.
4. DC-coupled stage providing additional gain and level shifting.
5. ADC driver with sufficient bandwidth and output drive capability.

Each stage’s gain, bandwidth, noise, and offset must be budgeted against the overall system specification.

12.2 Design Example: NMOS Amplifier

Specification. Midband voltage gain \( |A_v| \geq 10\,\text{V/V} \), \( f_H \geq 1\,\text{MHz} \), input resistance \( \geq 50\,\text{k}\Omega \), supply \( V_{DD} = 3.3\,\text{V} \).

Step 1: Choose topology. Common-source with resistive drain load. Gain is \( -g_m R_D \); input resistance is \( R_{G1}\|R_{G2} \).

Step 2: Choose Q-point. For gain \( g_m R_D \geq 10 \) and available \( V_{DD} = 3.3\,\text{V} \), choose \( V_{DS} = V_{DD}/2 \approx 1.65\,\text{V} \) (midpoint biasing for maximum symmetric swing). Voltage across \( R_D \) is \( 1.65\,\text{V} \). With \( I_D = 0.5\,\text{mA} \), \( R_D = 3.3\,\text{k}\Omega \).

Step 3: Compute \( g_m \). Need \( g_m \cdot 3.3\,\text{k}\Omega \geq 10 \), so \( g_m \geq 3.03\,\text{mA/V} \). Using \( g_m = \sqrt{2 k_n I_D} \), with typical \( k_n = 5\,\text{mA/V}^2 \): \( g_m = \sqrt{2 \times 5 \times 0.5} = \sqrt{5} \approx 2.24\,\text{mA/V} \). Adjust \( I_D \) upward to \( 1\,\text{mA} \): \( g_m = \sqrt{10} \approx 3.16\,\text{mA/V} \), \( R_D = 1.65\,\text{V}/1\,\text{mA} = 1.65\,\text{k}\Omega \). Gain check: \( 3.16 \times 1.65 = 5.21 \) — not enough. Increase \( R_D \) by allowing more voltage drop: try \( V_{DS} = 1\,\text{V} \), giving \( I_D R_D = 2.3\,\text{V} \), \( R_D = 2.3\,\text{k}\Omega \). Gain: \( 3.16 \times 2.3 = 7.27 \) — still not 10. Use \( k_n = 10\,\text{mA/V}^2 \) (wider transistor): \( g_m = \sqrt{20} \approx 4.47\,\text{mA/V} \), gain \( = 4.47 \times 2.3 \approx 10.3 \). Specification met.

Step 4: Set bias. \( V_S = I_D R_S \). Choose \( R_S = 300\,\Omega \) (0.3 V drop), so \( V_G = V_{GS} + V_S \). Compute \( V_{GS} = V_{tn} + V_{GS,ov} \); with \( V_{GS,ov} = \sqrt{2I_D/k_n} = \sqrt{0.2} \approx 0.447\,\text{V} \), assuming \( V_{tn} = 0.5\,\text{V} \): \( V_{GS} = 0.947\,\text{V} \), \( V_G = 0.947 + 0.3 = 1.247\,\text{V} \). Use voltage divider with \( R_{G1} + R_{G2} \leq V_{DD}/I_{div} \); for \( R_{in} \geq 50\,\text{k}\Omega \), ensure \( R_{G1}\|R_{G2} \geq 50\,\text{k}\Omega \).

Step 5: Bandwidth check. Compute \( f_H \) using SCTC. The Miller capacitance at the input is \( C_{gd}(1 + g_m R_D') \approx C_{gd} \times 11 \). With \( C_{gd} = 10\,\text{fF} \) and \( C_{gs} = 50\,\text{fF} \), the input time constant \( \tau_{in} = R_{sig}(C_{gs} + C_{gd}(1+g_m R_D')) \). For \( R_{sig} = 1\,\text{k}\Omega \): \( \tau_{in} = 1\,\text{k}\Omega \times (50 + 110)\,\text{fF} = 160\,\text{ps} \), giving \( f_H \approx 1\,\text{GHz} \) — well above the 1 MHz specification.