ECE 222: Digital Computers

Sources and References

Equivalent UW courses — CS 251 (Computer Organization and Design), CS 350 (Operating Systems — for the interrupt/OS-interface portion) Primary textbook — Patterson, David A., and John L. Hennessy. Computer Organization and Design: The Hardware/Software Interface, RISC-V Edition (2nd ed.). Morgan Kaufmann, 2020. Supplementary references — Harris and Harris, Digital Design and Computer Architecture: RISC-V Edition; RISC-V unprivileged ISA specification.

Equivalent UW Courses

ECE 222 is Computer Engineering’s introduction to computer organization and assembly-level programming. Its contents — instruction set architecture, assembly language, processor datapath and control, memory hierarchy, and basic I/O — line up almost one-to-one with CS 251, the course Computer Science students take to learn how a computer actually works beneath the C abstraction. Both courses now use Patterson and Hennessy as the textbook, although CS 251 has historically used the MIPS edition while ECE 222 uses the newer RISC-V edition. The interrupt-handling and I/O-driver material in ECE 222 also touches content that CS 350 develops more thoroughly on the OS side. In short, ECE 222 is essentially the engineering department’s CS 251 with a RISC-V accent.

What This Course Adds Beyond the Equivalents

ECE 222 leans harder on the hardware/embedded angle than CS 251. Labs typically involve programming a real microcontroller (often an ARM Cortex-M board in previous iterations, RISC-V in the current version), writing interrupt handlers, configuring peripherals, and reasoning about timing and I/O registers at the bare-metal level. CS 251 does more work inside MARS/RARS simulators and emphasizes the datapath on paper. ECE 222 also spends more time on exception and interrupt mechanisms — privilege levels, interrupt vectoring, and context-save — because those matter for subsequent ECE courses like ECE 350.

What ECE 222 omits relative to CS 251: less depth on floating-point representation and arithmetic algorithms, less emphasis on compiler translation patterns, and no MIPS-to-RISC-V comparison. It also does not cover the logic-design fundamentals (gates, flip-flops, FSMs) that ECE 124 handles earlier in the Computer Engineering sequence.

Topic Summary

Number Representation and Arithmetic

Binary, two’s-complement, and unsigned integer representations; sign extension and overflow. Binary addition, subtraction, shifting, and the structure of an arithmetic-logic unit. Brief treatment of IEEE 754 floating point at a descriptive level.

RISC-V Instruction Set Architecture

The RV32I base integer ISA: register file \( x_0 \)–\( x_{31} \), R/I/S/B/U/J instruction formats, and the core arithmetic, logical, load/store, and branch instructions. The invariant

\[ \texttt{x0} \equiv 0 \]

and the role of the link register for function calls. PC-relative addressing and the distinction between absolute and relative jumps.

Assembly Language Programming

Writing assembly by hand: pseudoinstructions, labels, directives, and the assembly/link/load pipeline. Calling conventions (caller-saved vs. callee-saved registers), stack-frame layout, argument passing, and recursion. Translating C control flow (if, while, switch) into branch sequences.

Processor Datapath and Control

Single-cycle datapath for a subset of RV32I: instruction fetch, decode, register read, ALU operation, memory access, writeback. Control signal generation from the opcode and funct fields. Performance comparison against a multicycle or pipelined implementation at a qualitative level.

Memory Hierarchy

Cache basics: direct-mapped, set-associative, and fully-associative organizations; block size, tag/index/offset decomposition; write-through vs. write-back and write-allocate policies. Average memory access time

\[ \text{AMAT} = t_{\text{hit}} + m \cdot t_{\text{miss}} \]

and the motivation for multiple cache levels. Virtual memory is introduced conceptually (pages, TLB) but full treatment is deferred to ECE 350.

Input/Output and Interrupts

Memory-mapped I/O vs. port-mapped I/O, polling vs. interrupt-driven designs, and DMA. The interrupt mechanism: saving state, jumping through a vector table, handling nested interrupts, and returning. Exceptions vs. interrupts and their common trap mechanism on RISC-V.

Labs

Assembly programming on a simulator followed by bare-metal work on a development board: configuring GPIO, timers, and UART; writing interrupt service routines; and measuring the effect of cache or pipeline behavior on simple benchmarks.