Sources and References

The technical content of these notes draws on the following publicly available references:

• A. S. Sedra, K. C. Smith, T. Chan Carusone, and V. Gaudet, Microelectronic Circuits, 8th ed., New York: Oxford University Press, 2020. (Primary required text for ECE 340.)
• B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., New York: McGraw-Hill, 2017. (Chapter 3 for MOS models; Chapter 10 for stability and compensation.)
• D. A. Neamen, Microelectronics: Circuit Analysis and Design, 4th ed., New York: McGraw-Hill, 2010. (Supplementary BJT amplifier analysis.)
• MIT OpenCourseWare 6.301 (Solid State Circuits), lecture materials on feedback amplifiers, stability, and op-amp design.
• P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 5th ed., New York: Wiley, 2009. (Advanced topics: current mirrors, noise, two-stage op amp analysis.)

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Chapter 1: Foundations — Amplifier Properties and Op-Amp Frequency Response

1.1 Amplifier Fundamentals Review

ECE 340 begins where ECE 240 concluded: with a working understanding of the ideal amplifier abstraction and its practical limitations. Before studying transistor-level implementations, it is essential to sharpen the conceptual tools used throughout the course.

An amplifier is a two-port network that accepts an input signal and delivers a scaled version to a load, drawing the additional energy from a dc power supply. The performance of any amplifier is characterised by four fundamental quantities: voltage gain \(A_v\), input resistance \(R_{in}\), output resistance \(R_{out}\), and bandwidth \(BW\). In integrated-circuit (IC) design, achieving all four simultaneously — high gain, high input resistance, low output resistance, wide bandwidth — under strict area and power constraints is the central engineering challenge.

The source resistance \(R_s\) similarly introduces voltage division at the input:

\[ v_i = v_s \cdot \frac{R_{in}}{R_{in} + R_s} \]

so that the overall gain from source to load is

\[ \frac{v_o}{v_s} = \frac{R_{in}}{R_{in} + R_s} \cdot A_{v0} \cdot \frac{R_L}{R_L + R_{out}} \]

This chain of voltage dividers motivates the IC designer to push \(R_{in}\) toward infinity and \(R_{out}\) toward zero.

1.2 The Ideal Operational Amplifier and Its Imperfections

The ideal op amp has infinite open-loop gain \(A\), infinite input resistance, zero output resistance, and infinite bandwidth. Real op amps deviate from this ideal in several important ways, all of which become dominant in the frequency range relevant to ECE 340.

1.2.1 Single-Pole Model of the Op Amp

The most important non-ideality for this course is the frequency dependence of the open-loop gain. A first-order (single-pole) model captures the dominant behaviour:

\[ A(s) = \frac{A_0}{1 + s/\omega_p} \]

where \(A_0\) is the dc open-loop gain (often \(10^5\) or higher) and \(\omega_p\) is the open-loop pole frequency (often a few radians per second for a compensated op amp). The magnitude of the open-loop gain rolls off at −20 dB/decade beyond \(\omega_p\).

1.2.2 Closed-Loop Gain and Bandwidth

Consider a non-inverting amplifier with feedback fraction \(\beta = R_1/(R_1 + R_2)\). The closed-loop gain is

\[ A_{CL}(s) = \frac{A(s)}{1 + \beta A(s)} \]

Substituting the single-pole model:

\[ A_{CL}(s) = \frac{A_0 / (1 + A_0 \beta)}{1 + s / [\omega_p(1 + A_0 \beta)]} \]

The closed-loop dc gain is \(A_{CL,0} = A_0/(1+A_0\beta) \approx 1/\beta\) for \(A_0\beta \gg 1\), and the closed-loop bandwidth is

\[ \omega_{CL} = \omega_p (1 + A_0 \beta) \approx A_0 \beta \omega_p = \beta \omega_t \]

1.2.3 Slew Rate and Full-Power Bandwidth

Beyond small-signal bandwidth, large-signal operation introduces the slew rate \(SR\), the maximum rate of change of the output voltage:

\[ SR = \frac{dv_o}{dt}\bigg|_{max} \]

For a sinusoidal output \(v_o = V_m \sin(\omega t)\), the maximum rate of change is \(V_m \omega\). The full-power bandwidth is the highest frequency at which the amplifier can produce a full-swing sinusoid without slew-rate distortion:

\[ f_{FP} = \frac{SR}{2\pi V_m} \]

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Chapter 2: MOSFET Amplifiers — Single-Stage Analysis and Design

2.1 Review of MOSFET Small-Signal Models

The MOSFET operates in saturation when \(V_{DS} \geq V_{GS} - V_{tn}\) (for NMOS). In this region, the drain current is

\[ I_D = \frac{1}{2} \mu_n C_{ox} \frac{W}{L} (V_{GS} - V_{tn})^2 (1 + \lambda V_{DS}) \]

where \(\mu_n\) is the electron mobility, \(C_{ox}\) the gate-oxide capacitance per unit area, \(W/L\) the aspect ratio, \(V_{tn}\) the threshold voltage, and \(\lambda\) the channel-length modulation parameter.

The small-signal transconductance, evaluated at the dc operating point \(Q = (V_{GS,Q}, I_{D,Q})\), is

\[ g_m = \frac{\partial I_D}{\partial V_{GS}}\bigg|_Q = \mu_n C_{ox} \frac{W}{L} (V_{GS,Q} - V_{tn}) = \sqrt{2 \mu_n C_{ox} \frac{W}{L} I_{D,Q}} \]

The output resistance, capturing the effect of channel-length modulation, is

\[ r_o = \frac{1}{\lambda I_{D,Q}} \approx \frac{|V_A|}{I_{D,Q}} \]

where \(V_A = 1/\lambda\) is the Early voltage.

2.1.1 The T-Model vs. the Hybrid-\(\pi\) Model

Two equivalent small-signal models are in common use. The hybrid-\(\pi\) model places a voltage-controlled current source \(g_m v_{gs}\) between drain and source, with \(r_o\) in parallel. The T-model places a source resistance \(1/g_m\) in series with the source terminal and a current source \(g_m v_{gs}\) from drain to source. Both are equivalent; the choice depends on circuit topology.

2.2 DC Bias and Operating Point

For an NMOS transistor biased with resistors \(R_{G1}\) and \(R_{G2}\) forming a voltage divider, and a source resistor \(R_S\):

\[ V_G = V_{DD} \frac{R_{G2}}{R_{G1} + R_{G2}}, \quad V_{GS} = V_G - I_D R_S \]

Substituting into the saturation current equation yields a quadratic in \(I_D\). The stable solution with \(V_{GS} > V_{tn}\) gives the Q-point. A well-designed bias sets \(I_{D,Q}\) to achieve the required \(g_m\) and \(r_o\).

2.3 Common-Source Amplifier

The common-source (CS) configuration is the workhorse of MOSFET amplification. With drain resistance \(R_D\) and ignoring body effect:

\[ A_v = -g_m (R_D \| r_o) \]\[ R_{in} = R_{G1} \| R_{G2} \quad (\text{at the gate}) \]\[ R_{out} = R_D \| r_o \]

Adding a source degeneration resistor \(R_S\) introduces series-series feedback (see Chapter 7), reducing gain while improving linearity:

\[ A_v \approx \frac{-g_m R_D}{1 + g_m R_S}, \quad R_{out} \approx R_D \]

2.4 Common-Gate Amplifier

The common-gate (CG) configuration drives current into the source terminal and takes output at the drain. Key parameters:

\[ A_v = g_m (R_D \| r_o) \approx g_m R_D \]\[ R_{in} = \frac{1}{g_m} \| r_o \approx \frac{1}{g_m} \]\[ R_{out} = R_D \| r_o \]

The low input resistance of the CG stage makes it well-suited for current sensing and as the upper transistor in a cascode configuration.

2.5 Common-Drain (Source Follower) Amplifier

The source follower presents high input resistance and low output resistance, making it the canonical voltage buffer in CMOS design:

\[ A_v = \frac{g_m r_o}{1 + g_m r_o} \approx 1 - \frac{1}{g_m r_o} < 1 \]\[ R_{out} = \frac{1}{g_m} \| r_o \approx \frac{1}{g_m} \]

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Chapter 3: Integrated-Circuit Building Blocks

3.1 Current Mirrors

Current mirrors are the fundamental biasing element in analog ICs. Unlike discrete circuits that rely on resistors, IC processes prefer transistor-based current references because they occupy less area, exhibit better temperature tracking, and can be mirrored to multiple branches.

3.1.1 Basic MOSFET Current Mirror

The simplest current mirror consists of a diode-connected reference transistor \(M_1\) and a mirror transistor \(M_2\). The reference current \(I_{REF}\) flows through \(M_1\), setting \(V_{GS} = V_{GS1}\). Because \(V_{GS2} = V_{GS1}\) (shared gate–source connection), the output current is

\[ I_O = \frac{(W/L)_2}{(W/L)_1} I_{REF} \]

assuming both transistors are in saturation. The ratio \((W/L)_2 / (W/L)_1\) is called the mirror ratio, and can be set by layout to achieve \(I_O = N \cdot I_{REF}\).

3.1.2 Cascode Current Mirror

The cascode current mirror eliminates the \(\lambda\)-related error by enforcing equal \(V_{DS}\) on both reference and mirror transistors. Adding a cascode transistor \(M_3\) on the mirror side, with its gate biased so that \(V_{DS2} = V_{DS1}\):

\[ I_O \approx \frac{(W/L)_2}{(W/L)_1} I_{REF} \left(1 + \lambda \Delta V_{DS}\right) \]

where \(\Delta V_{DS} \approx 0\) by design. The output resistance of the cascode mirror is dramatically increased:

\[ R_{out,cascode} \approx g_{m3} r_{o3} r_{o2} \]

This high output resistance is exploited in high-gain amplifier stages.

3.1.3 Wilson and Widlar Current Mirrors

The Wilson mirror uses feedback to reduce current error without requiring a separate bias. The Widlar mirror adds an emitter (or source) degeneration resistor to the mirror transistor alone, producing a sub-threshold or very small output current from a larger reference:

\[ I_O = \frac{V_T \ln(I_{REF}/I_O)}{R_S} \quad \text{(BJT Widlar)} \]

This is solved transcendentally but permits nanoampere output currents from microampere references in ultra-low-power designs.

3.2 Active Loads

An active load replaces the drain resistor \(R_D\) of a CS amplifier with a PMOS current-source transistor. The active load presents a very high incremental resistance (\(r_{o,P}\)) to the signal, while conducting a well-defined dc bias current. The voltage gain of a CS stage with an active load becomes

\[ A_v = -g_m (r_{o,N} \| r_{o,P}) \]

Since \(r_o \gg R_D\) for a practical resistor, gains of several hundred are achievable in a single stage with an active load — impossible with resistive loading at low supply voltages.

3.3 The Cascode Amplifier

The cascode configuration stacks a CG transistor \(M_2\) above a CS transistor \(M_1\). The CS transistor provides transconductance; the CG transistor provides high output resistance and dramatically reduces the Miller effect on the CS input capacitance.

3.3.1 Gain and Output Resistance

With a resistive drain load \(R_D\), the cascode voltage gain is approximately

\[ A_v \approx -g_{m1} R_{out} \]

where the output resistance of the cascode is

\[ R_{out} \approx g_{m2} r_{o2} r_{o1} \]

exceeding the simple CS output resistance by a factor \(g_{m2} r_{o2} \gg 1\). Combining a cascode amplifier with a cascode active load yields a telescopic cascode whose gain is

\[ A_v \approx -g_{m1} (g_{m2} r_{o2} r_{o1} \| g_{m4} r_{o4} r_{o3}) \]

Gains of \(10^4\)–\(10^5\) V/V are achievable, forming the core of many op-amp first stages.

3.3.2 Voltage Headroom

The cascode penalty is reduced voltage swing. Each transistor must remain in saturation, so the minimum output voltage is

\[ V_{out,min} \approx V_{OV1} + V_{OV2} \]

where \(V_{OV} = V_{GS} - V_t\) is the overdrive voltage. Low-voltage cascode bias techniques (self-biased cascodes, regulated cascodes) address this constraint.

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Chapter 4: BJT Circuits and Single-BJT Amplifiers

4.1 BJT Small-Signal Model

The bipolar junction transistor (BJT) is modelled in small signal by the hybrid-\(\pi\) equivalent circuit. The key parameters are:

• Transconductance: \(g_m = I_C / V_T\) where \(V_T = kT/q \approx 26\) mV at room temperature.
• Base–emitter resistance: \(r_\pi = \beta / g_m = V_T / I_B\).
• Output resistance: \(r_o = V_A / I_C\) (BJT Early voltage).
• Base resistance: \(r_x\) (series resistance of the base contact, significant at high frequency).

4.2 Single-Stage BJT Amplifiers

4.2.1 Common-Emitter Amplifier

Analogous to the MOSFET common-source, the common-emitter (CE) stage delivers inverting voltage gain:

\[ A_v = -g_m (R_C \| r_o) \approx -\frac{I_C R_C}{V_T} \]\[ R_{in} = R_{B1} \| R_{B2} \| r_\pi, \quad R_{out} = R_C \| r_o \]

Emitter degeneration with \(R_E\) reduces gain but improves linearity and stabilises the Q-point:

\[ A_v \approx \frac{-g_m R_C}{1 + g_m R_E} \approx \frac{-R_C}{R_E} \quad (g_m R_E \gg 1) \]

4.2.2 Common-Base and Common-Collector Amplifiers

The common-base (CB) stage has \(R_{in} \approx 1/g_m \approx V_T/I_C\), a very low input resistance useful for current-to-voltage conversion and high-frequency operation. The emitter follower (CC) is the BJT analogue of the source follower, with \(A_v \lesssim 1\) and low \(R_{out} \approx 1/g_m\).

4.3 The BJT Cascode

A CE–CB cascade (cascode) benefits from the CE transconductance and the CB’s high output resistance and bandwidth. The voltage gain equals

\[ A_v = -g_{m,CE} \cdot (g_{m,CB} r_{o,CB} r_{o,CE} \| R_C) \]

and the input resistance is that of the CE base, \(r_\pi\), without the penalty of the Miller effect present in a simple CE stage.

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Chapter 5: Differential-Pair Amplifiers

5.1 The MOS Differential Pair

The differential pair is the most important circuit topology in analog IC design. It forms the input stage of virtually every op amp and comparator, and its rejection of common-mode signals is critical in noisy environments.

5.1.1 Large-Signal Analysis

Two NMOS transistors \(M_1\) and \(M_2\) share a tail current source \(I_{SS}\). With differential input \(v_{id} = v_{G1} - v_{G2}\):

\[ i_{D1} - i_{D2} = \frac{1}{2} \mu_n C_{ox} \frac{W}{L} v_{id} \sqrt{V_{OV}^2 - (v_{id}/2)^2} \]

where \(V_{OV} = \sqrt{I_{SS}/(\mu_n C_{ox} W/L)}\) is the common overdrive. For linear operation, \(|v_{id}| \ll \sqrt{2} V_{OV}\). The differential pair steers all of \(I_{SS}\) to one side when \(|v_{id}| > \sqrt{2} V_{OV}\).

5.1.2 Small-Signal Analysis

For \(|v_{id}|\) small, the half-circuit technique applies. The differential-mode half-circuit is a CS stage with gain:

\[ A_d = \frac{v_{od}}{v_{id}} = -g_m (R_D \| r_o) \]

where \(g_m = \sqrt{\mu_n C_{ox} (W/L) I_{SS}/2}\) is the transconductance of each transistor biased at \(I_{SS}/2\).

5.1.3 Common-Mode Rejection

The common-mode half-circuit places \(2R_{SS}\) (twice the tail-current-source impedance) in the source. The common-mode gain is

\[ A_{cm} = \frac{-g_m R_D}{1 + 2 g_m R_{SS}} \approx \frac{-R_D}{2 R_{SS}} \]

The common-mode rejection ratio (CMRR) is defined as

\[ CMRR = \left|\frac{A_d}{A_{cm}}\right| = g_m R_{SS} \cdot \left(\frac{R_D}{r_o}\right)^{-1} \approx 2 g_m R_{SS} \]

A high-impedance tail current source (cascode or regulated cascode) maximises \(R_{SS}\) and therefore CMRR.

5.2 Active-Load Differential Pair

Replacing the differential drain resistors with a PMOS current mirror (active load) converts the differential output to a single-ended output while doubling the effective transconductance. This is accomplished because the mirror reflects the drain current of \(M_1\) and adds it in the same direction as the drain current of \(M_2\) at the output node.

The single-ended differential gain becomes

\[ A_d = -g_m (r_{o,N} \| r_{o,P}) \]

which equals the gain of a cascode stage with a resistive load \(r_{oN} \| r_{oP}\). The active-load pair is the standard first stage of the two-stage CMOS op amp.

5.3 BJT Differential Pair

The bipolar differential pair functions identically, with \(g_m = I_C/V_T\) and \(r_\pi = \beta/g_m\). The input resistance of the BJT differential pair is much lower than for MOSFET: \(R_{id} = 2 r_\pi\), which loads the signal source. This is the principal disadvantage of BJT input stages compared to MOSFET.

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Chapter 6: Frequency Response of Amplifiers

6.1 Coupling and Bypass Capacitors — Low-Frequency Response

In discrete amplifier designs, large coupling capacitors \(C_C\) and bypass capacitors \(C_E\) or \(C_S\) create low-frequency poles. The lower −3 dB frequency \(\omega_L\) is dominated by the largest time constant, which corresponds to the smallest capacitor (all in series or shunt with appropriate resistances). In IC amplifiers, there are no coupling capacitors; the low-frequency response extends to dc, making \(\omega_L = 0\).

6.2 High-Frequency Response — Transistor Capacitances

At high frequency, the intrinsic capacitances of the transistor limit gain. For a MOSFET in saturation:

• Gate-source capacitance: \(C_{gs} = \frac{2}{3} W L C_{ox} + C_{ov}\) (includes overlap capacitance \(C_{ov} = W C_{ox,ov}\))
• Gate-drain capacitance: \(C_{gd} = C_{ov}\) (overlap only in saturation)
• Source-body and drain-body capacitances: \(C_{sb}\), \(C_{db}\) (junction capacitances)

For a BJT:

• Base-emitter capacitance: \(C_\pi = g_m \tau_F + C_{je}\) where \(\tau_F\) is the forward transit time
• Base-collector capacitance: \(C_\mu\) (collector–base junction, reverse biased)

6.3 Miller’s Theorem

Miller’s theorem addresses the difficulty posed by \(C_{gd}\) (or \(C_\mu\) in BJTs): a capacitor bridging input and output of an inverting amplifier appears — from the input — as a much larger capacitor to ground.

The Miller capacitance \(C_{M1} = C_{gd}(1 + |A_v|)\) at the input can be very large, severely limiting bandwidth. This is the Miller effect, and it motivates the cascode topology as a bandwidth enhancement technique (the CG transistor reduces the voltage swing at the CS drain, making \(|A_v| \approx 1\) for the CS stage and thus \(C_{M1} \approx 2 C_{gd}\)).

6.4 Open-Circuit Time Constant Method

Rather than computing the full transfer function (which requires solving for all poles simultaneously), the open-circuit time constant (OCT) method estimates the upper −3 dB frequency efficiently.

The OCT method is accurate when one time constant dominates (i.e., one pole is much lower than all others). It becomes less accurate when poles are closely spaced.

6.4.1 Applying OCT to the CS Amplifier

For a CS stage with \(C_{gs}\), \(C_{gd}\), and \(C_L\) (load capacitance), with source resistance \(R_{sig}\) and drain resistance \(R_D\):

\[ \tau_{gs} = C_{gs} R_{sig} \]\[ \tau_{gd} = C_{gd} [R_{sig}(1 + g_m R_D) + R_D] = C_{gd} R_{gd}^0 \]\[ \tau_L = C_L R_D \]

The Miller factor \((1 + g_m R_D)\) in \(\tau_{gd}\) confirms that \(C_{gd}\) makes the dominant contribution to bandwidth limitation when gain is high.

\[ \omega_H \approx \frac{1}{\tau_{gs} + \tau_{gd} + \tau_L} \]

6.5 Short-Circuit Time Constant Method for Low-Frequency Poles

The dual of OCT is the short-circuit time constant (SCT) method, used for low-frequency poles due to coupling and bypass capacitors. The lower −3 dB frequency is approximated by

\[ \omega_L \approx \sum_{i=1}^n \frac{1}{R_i^{\infty} C_i} \]

where \(R_i^{\infty}\) is the resistance seen by \(C_i\) when all other coupling/bypass capacitors are short-circuited.

6.6 Unity-Gain Frequency \(f_T\) of the Transistor

The intrinsic figure of merit for a transistor’s high-frequency capability is \(f_T\), the frequency at which the short-circuit current gain \(h_{fe}\) (for BJT) or the short-circuit transconductance current gain (for MOSFET) falls to unity.

6.6.1 BJT \(f_T\)

With the output short-circuited at the collector, the base current flows through \(r_\pi\) and \(C_\pi + C_\mu\). The collector current is \(g_m v_\pi\). Setting the current gain to unity:

\[ f_T = \frac{g_m}{2\pi (C_\pi + C_\mu)} = \frac{1}{2\pi \tau_T} \]

where \(\tau_T = \tau_F + C_{je}/(g_m) + C_\mu/(g_m)\) is the total transit time.

6.6.2 MOSFET \(f_T\)

\[ f_T = \frac{g_m}{2\pi (C_{gs} + C_{gd})} \approx \frac{3 \mu_n V_{OV}}{4\pi L^2} \]

This result shows that \(f_T \propto \mu_n/L^2\), motivating the relentless reduction of channel length in advanced CMOS processes.

6.7 Frequency Response of the Cascode Amplifier

The cascode dramatically reduces the Miller effect. The CS device \(M_1\) sees a low impedance at its drain (the input of the CG device \(M_2\)), so the voltage gain of the CS stage alone is

\[ A_{v,CS} \approx -g_{m1}/g_{m2} \approx -1 \quad \text{(for matched transistors)} \]

The Miller multiplication of \(C_{gd1}\) is therefore \((1 + 1) = 2\) rather than \((1 + g_m R_D)\). The bandwidth improvement factor is approximately

\[ \frac{BW_{cascode}}{BW_{CS}} \approx \frac{g_m R_D}{2} \]

This can be tens to hundreds in practical designs.

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Chapter 7: Multi-Stage Amplifiers and the Two-Stage CMOS Op Amp

7.1 Cascaded Amplifier Stages

A cascade of \(n\) identical amplifier stages, each with gain \(|A_v|\) and upper −3 dB frequency \(f_H\), has an overall bandwidth that shrinks with each added stage:

\[ f_{H,n} = f_H \sqrt{2^{1/n} - 1} \]

This bandwidth shrinkage means that large total gain must be achieved with as few stages as possible, motivating high-gain single stages (cascode, active load) over many low-gain stages.

7.2 The Two-Stage CMOS Op Amp

The most common CMOS op-amp topology consists of:

1. A differential-pair first stage with active load (PMOS current mirror), providing high differential gain and converting to single-ended output.
2. A CS second stage (common-source with PMOS load), providing additional voltage gain.
3. A frequency compensation network, typically a Miller capacitor \(C_C\) connected between the second-stage output and the gate of the second-stage transistor.

7.2.1 Open-Loop Gain

The total open-loop gain is

\[ A_0 = A_{v1} \cdot A_{v2} = g_{m1}(r_{o2} \| r_{o4}) \cdot g_{m6}(r_{o6} \| r_{o7}) \]

where \(M_1\)–\(M_4\) form the first stage and \(M_6\)–\(M_7\) the second stage.

7.2.2 Miller Frequency Compensation

The compensation capacitor \(C_C\) creates a dominant pole at the output of the first stage:

\[ \omega_{p1} \approx \frac{1}{g_{m6} R_1 R_2 C_C} \]

where \(R_1 = r_{o2} \| r_{o4}\) and \(R_2 = r_{o6} \| r_{o7}\). This pole is pushed to a very low frequency, ensuring unity-gain crossover occurs well before the second pole at the second-stage output:

\[ \omega_{p2} \approx \frac{g_{m6}}{C_L} \]

The unity-gain frequency is

\[ \omega_t \approx g_{m1} / C_C \]

For stability with 45° phase margin, we require \(\omega_t \leq \omega_{p2}\), giving the design constraint

\[ C_C \geq g_{m1} C_L / g_{m6} \]

7.2.3 Right-Half-Plane Zero

Miller compensation introduces a right-half-plane (RHP) zero at

\[ \omega_z = g_{m6}/C_C \]

because \(C_C\) provides a signal feedforward path (through \(C_C\) directly) that arrives at the output in phase with the input, creating a zero in the numerator. This RHP zero contributes positive phase shift below \(\omega_z\) but acts like a second pole in magnitude (it causes the gain to roll off faster while adding phase lag). The RHP zero is eliminated by inserting a series resistor \(R_z = 1/g_{m6}\) in series with \(C_C\), which pushes the zero to infinity.

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Chapter 8: Feedback in Amplifier Circuits

8.1 The Feedback Concept

Negative feedback is the most powerful tool in linear amplifier design. It trades gain for predictability, stability, and improved performance metrics. The fundamental feedback equation, derived by Black in 1934, is:

\[ A_f = \frac{A}{1 + A\beta} \]

where \(A\) is the open-loop gain, \(\beta\) is the feedback fraction, and \(A\beta\) is the loop gain \(T\). The quantity \(1 + T\) is called the feedback factor or desensitivity factor.

8.2 The Four Feedback Topologies

The type of connection at the input and output of the feedback network determines the topology. The output quantity sampled is either voltage (shunt at output) or current (series at output). The feedback signal returned to the input is either voltage (series at input) or current (shunt at input).

8.2.1 Series-Shunt (Voltage Amplifier Feedback)

• Output: voltage sampled (shunt connection)
• Input: voltage feedback signal in series with input

The feedback fraction \(\beta = R_1/(R_1+R_2)\) is dimensionless. Effects of feedback:

\[ R_{in,f} = R_{in}(1+T), \quad R_{out,f} = \frac{R_{out}}{1+T} \]

The non-inverting op-amp configuration is the prototype series-shunt feedback amplifier.

8.2.2 Shunt-Shunt (Transresistance Feedback)

• Output: voltage sampled (shunt)
• Input: current feedback signal in shunt with input

The closed-loop transresistance is \(R_{m,f} = R_m/(1+T)\). Effects:

\[ R_{in,f} = \frac{R_{in}}{1+T}, \quad R_{out,f} = \frac{R_{out}}{1+T} \]

The inverting amplifier with resistor from output to input node is the prototype shunt-shunt circuit. The feedback resistor \(R_f\) samples the output voltage and returns a current to the virtual ground at the inverting input.

8.2.3 Series-Series (Transconductance Feedback)

• Output: current sampled (series)
• Input: voltage feedback in series

The closed-loop transconductance is \(G_{m,f} = G_m/(1+T)\). Effects:

\[ R_{in,f} = R_{in}(1+T), \quad R_{out,f} = R_{out}(1+T) \]

This topology stabilises output current against load variations, ideal for voltage-to-current converters.

8.2.4 Shunt-Series (Current Amplifier Feedback)

• Output: current sampled (series)
• Input: current feedback in shunt

The closed-loop current gain is \(A_{i,f} = A_i/(1+T)\). Effects:

\[ R_{in,f} = \frac{R_{in}}{1+T}, \quad R_{out,f} = R_{out}(1+T) \]

8.2.5 Summary Table

Topology	Samples	Returns	\(R_{in,f}\)	\(R_{out,f}\)
Series-shunt	Voltage	Voltage	\(R_{in}(1+T)\)	\(R_{out}/(1+T)\)
Shunt-shunt	Voltage	Current	\(R_{in}/(1+T)\)	\(R_{out}/(1+T)\)
Series-series	Current	Voltage	\(R_{in}(1+T)\)	\(R_{out}(1+T)\)
Shunt-series	Current	Current	\(R_{in}/(1+T)\)	\(R_{out}(1+T)\)

8.3 Loop Gain Computation — Blackman’s Formula and Return Ratio

For a two-port feedback network approach, the feedback is identified by breaking the loop at a convenient point, injecting a test signal, and computing the returned signal. The loop gain is

\[ T = \beta A \]

where \(A\) is the forward gain of the amplifier with the feedback network loading it at both input and output, and \(\beta\) is the reverse transmission of the feedback network.

8.4 Feedback and Stability

The loop gain \(T(s)\) is frequency-dependent because \(A(s)\) contains poles. If \(|T(j\omega)| = 1\) at a frequency where \(\angle T(j\omega) = -180°\), the feedback becomes positive and the amplifier oscillates.

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Chapter 9: Stability and Frequency Compensation

9.1 The Nyquist Stability Criterion

The Nyquist criterion provides a rigorous test for closed-loop stability based on the open-loop frequency response. For a unity-feedback system with loop gain \(T(s)\):

Equivalently, on a Bode plot: the closed-loop system is stable if, at the gain crossover frequency \(\omega_{gc}\) where \(|T(j\omega_{gc})| = 1\) (0 dB), the phase of \(T(j\omega_{gc})\) is greater than \(-180°\).

9.2 Phase Margin and Gain Margin

9.3 Bode Plot Analysis for Multi-Pole Systems

A two-stage op amp without compensation has two significant poles. The loop gain is

\[ T(s) = \frac{A_0}{\left(1 + s/\omega_{p1}\right)\left(1 + s/\omega_{p2}\right)} \]

The phase at the unity-gain crossover \(\omega_t\) is

\[ \angle T(j\omega_t) = -\arctan(\omega_t/\omega_{p1}) - \arctan(\omega_t/\omega_{p2}) \]

For a phase margin of 45°, we need \(\arctan(\omega_t/\omega_{p1}) + \arctan(\omega_t/\omega_{p2}) < 135°\). Without compensation, a two-pole system with \(\omega_{p2} \approx \omega_{p1}\) will have approximately 180° of phase at crossover, giving 0° PM and marginal stability.

9.4 Dominant Pole Compensation

Dominant pole compensation deliberately introduces a new low-frequency pole \(\omega_{pd} \ll \omega_{p1}\), pushing the unity-gain crossover below \(\omega_{p1}\) so that only one pole has significant phase contribution at crossover.

The compensated loop gain is

\[ T_c(s) = \frac{A_0}{\left(1 + s/\omega_{pd}\right)\left(1 + s/\omega_{p1}\right)\left(1 + s/\omega_{p2}\right)} \]

Choosing \(\omega_{pd}\) so that \(A_0 \omega_{pd} = \omega_{gc} \ll \omega_{p1}\) ensures PM ≈ 90° − arctan(\(\omega_{gc}/\omega_{p1}\)) > 45°.

The cost: dramatically reduced bandwidth. The unity-gain frequency drops from \(\sim\sqrt{A_0 \omega_{p1} \omega_{p2}}\) to \(A_0 \omega_{pd}\).

9.5 Miller Compensation (Pole Splitting)

In the two-stage CMOS op amp, Miller compensation connects \(C_C\) between the second-stage output and gate. This achieves pole splitting: the compensation capacitor pushes the first pole to lower frequencies and the second pole to higher frequencies.

The compensated poles are approximately:

\[ \omega_{p1}' \approx \frac{1}{g_{m6} R_1 R_2 C_C} \]\[ \omega_{p2}' \approx \frac{g_{m6}}{C_2} \cdot \frac{C_C + C_1}{C_1} \approx \frac{g_{m6}}{C_L} \]

where \(C_1\) is the parasitic capacitance at the first-stage output and \(C_2 = C_L\) is the load capacitance at the second-stage output.

The unity-gain frequency is \(\omega_t = g_{m1}/C_C\). For PM ≥ 60°, we need

\[ \omega_t \leq \frac{\omega_{p2}'}{(tan(90° - 60°))} = \omega_{p2}' \cdot \tan(30°) \approx 0.577 \omega_{p2}' \]

yielding the design rule \(C_C \geq 0.577 \cdot g_{m1} C_L / g_{m6}\).

9.6 Lead Compensation

Lead compensation adds a zero to the loop gain at frequency \(\omega_z < \omega_{gc}\), contributing positive phase at the gain crossover. A lead network implemented as \(R_z\) in series with \(C_C\) moves the RHP zero to the left half-plane:

\[ \omega_z = \frac{1}{R_z C_C - C_C/g_{m6}} = \frac{g_{m6}}{g_{m6} R_z C_C - C_C} \]

Setting \(R_z = 1/g_{m6}\) pushes \(\omega_z \to \infty\). Setting \(R_z > 1/g_{m6}\) creates an LHP zero that adds positive phase and aids stability.

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Chapter 10: Output Stages and Power Amplifiers

10.1 Classification of Amplifier Classes

Power amplifiers are classified by the fraction of the input cycle during which the active device conducts:

• Class A: Device conducts for the full cycle (360°). Quiescent current \(I_Q \geq I_{out,peak}\). Maximum theoretical efficiency: 25% (resistive load) or 50% (with inductor/transformer).
• Class B: Two complementary devices each conduct for half the cycle (180°). Quiescent current \(I_Q = 0\). Theoretical maximum efficiency: 78.5%.
• Class AB: A small quiescent current is maintained, so each device conducts slightly more than 180°. Eliminates crossover distortion while approaching Class B efficiency.
• Class C: Conduction angle < 180°; used in RF tuned amplifiers.
• Class D: Switching amplifier with pulse-width modulation; theoretical efficiency approaching 100%.

10.2 Class A Output Stage

The emitter follower (CE configuration with large bypass capacitor at base) or source follower is a classic Class A output stage. For a resistive load \(R_L\), the quiescent drain/collector current must be at least \(V_{out,peak}/R_L\) to prevent clipping on the negative swing:

\[ P_{dc} = V_{CC} I_Q, \quad P_{load} = \frac{V_{out,peak}^2}{2R_L} \]\[ \eta = \frac{P_{load}}{P_{dc}} = \frac{V_{out,peak}^2}{2 R_L V_{CC} I_Q} \]

Maximum efficiency occurs when \(V_{out,peak} \to V_{CC}\) and \(I_Q \to V_{CC}/(2R_L)\), giving \(\eta_{max} = 25\%\).

10.3 Class B Push-Pull Stage

The complementary push-pull stage uses an NPNP or NMOS/PMOS pair. For a sinusoidal output \(v_o = V_m \sin(\omega t)\):

• During positive half-cycle: NMOS (or NPN) conducts, PMOS (or PNP) is off.
• During negative half-cycle: PMOS (or PNP) conducts, NMOS (or NPN) is off.

The dc power drawn is

\[ P_{dc} = \frac{2 V_{CC} V_m}{\pi R_L} \]

The load power is

\[ P_L = \frac{V_m^2}{2 R_L} \]

The efficiency is

\[ \eta = \frac{\pi V_m}{4 V_{CC}} \]

Maximum efficiency when \(V_m \to V_{CC}\): \(\eta_{max} = \pi/4 \approx 78.5\%\).

10.3.1 Crossover Distortion

Because the MOSFET (or BJT) requires a threshold voltage \(V_t\) (or \(V_{BE} \approx 0.6\) V) to begin conducting, there is a dead zone around zero input where neither device conducts. This creates crossover distortion, a highly nonlinear distortion that is most audible at low signal levels.

10.4 Class AB Operation

Biasing the output devices with a small quiescent current \(I_Q\) (typically a few milliamperes for audio applications) eliminates the dead zone. The bias is provided by a \(V_{BE}\) multiplier circuit or, in CMOS, by a current-mirror biased pair.

The output stage is typically enclosed in the negative feedback loop of the op amp, which further reduces distortion to negligible levels.

10.5 Thermal Considerations

Power dissipation in the output transistors raises junction temperature. The thermal model is analogous to an electrical circuit:

\[ T_J = T_A + P_D (\theta_{JC} + \theta_{CS} + \theta_{SA}) \]

where \(\theta_{JC}\), \(\theta_{CS}\), \(\theta_{SA}\) are the junction-to-case, case-to-sink, and sink-to-ambient thermal resistances (°C/W). For safe operation, \(T_J < T_{J,max}\) (typically 150°C for silicon). The maximum allowable power dissipation is

\[ P_{D,max} = \frac{T_{J,max} - T_A}{\theta_{JC} + \theta_{CS} + \theta_{SA}} \]

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Chapter 11: Voltage Regulators

11.1 Linear Voltage Regulators

11.1.1 Series-Pass Regulator

A series-pass (or series linear) regulator places a transistor between the unregulated supply \(V_{in}\) and the regulated output \(V_{out}\). The transistor acts as a variable resistor that absorbs the voltage difference \(V_{in} - V_{out}\), maintaining \(V_{out}\) constant.

The regulation is achieved by a feedback amplifier that monitors \(V_{out}\) via a resistive divider and drives the control terminal of the pass transistor:

\[ V_{out} = V_{ref} \left(1 + \frac{R_1}{R_2}\right) \]

where \(V_{ref}\) is a stable reference voltage (typically from a bandgap reference).

The load regulation is

\[ \frac{\Delta V_{out}}{\Delta I_L} = \frac{R_{out,pass}}{1 + A_0 \beta} \]

where \(A_0\) is the error amplifier gain and \(\beta = R_2/(R_1+R_2)\).

The efficiency of a linear regulator is simply

\[ \eta = \frac{V_{out} I_L}{V_{in} I_{in}} \approx \frac{V_{out}}{V_{in}} \]

For \(V_{in} = 5\) V, \(V_{out} = 1.8\) V, the maximum efficiency is only 36%. This limitation drives the adoption of switching regulators in battery-powered applications.

11.1.2 Low-Dropout (LDO) Regulators

A conventional NPN series-pass regulator requires \(V_{in} > V_{out} + V_{BE} + V_{CE,sat} \approx 2\) V. An LDO uses a PMOS pass transistor, which only needs \(V_{in} > V_{out} + V_{DS,sat} \approx V_{out} + 200\) mV.

The PMOS LDO has a stability challenge: the pass transistor forms a second gain stage, and the loop has two poles (one at the error amplifier output and one at the output node). The output capacitor \(C_{out}\) and its equivalent series resistance (ESR) \(R_{ESR}\) create an LHP zero at \(1/(R_{ESR} C_{out})\) that aids stability by adding phase at the gain crossover.

11.2 Switching Regulators

Switching regulators achieve high efficiency (typically 85–95%) by operating the pass transistor as a switch — fully on or fully off — and using reactive elements (inductors, capacitors) to filter the switched waveform.

11.2.1 Buck (Step-Down) Converter

The buck converter steps down voltage from \(V_{in}\) to \(V_{out} < V_{in}\). A switch \(S\) and freewheeling diode (or synchronous switch) alternate to apply rectangular pulses to an LC filter.

In steady state (continuous conduction mode, CCM), volt-second balance on the inductor gives

\[ V_{out} = D \cdot V_{in} \]

where \(D = t_{on}/T\) is the duty cycle and \(T\) is the switching period. The duty cycle is adjusted by pulse-width modulation (PWM) to regulate \(V_{out}\) against load and line variations.

The inductor current ripple is

\[ \Delta I_L = \frac{(V_{in} - V_{out}) D T}{L} = \frac{V_{out}(1-D)}{f_s L} \]

where \(f_s = 1/T\) is the switching frequency. Increasing \(f_s\) or \(L\) reduces ripple.

The output voltage ripple is set by the capacitor charge balance:

\[ \Delta V_{out} = \frac{\Delta I_L}{8 f_s C_{out}} \]

11.2.2 Boost (Step-Up) Converter

The boost converter steps up voltage from \(V_{in}\) to \(V_{out} > V_{in}\). During the on-time, the switch connects the inductor to ground; energy is stored. During the off-time, the inductor delivers stored energy through the diode to the output capacitor.

Volt-second balance:

\[ V_{in} D T = (V_{out} - V_{in})(1-D) T \]\[ V_{out} = \frac{V_{in}}{1-D} \]

As \(D \to 1\), \(V_{out} \to \infty\) in the ideal case. In practice, parasitic resistances limit the maximum conversion ratio.

11.2.3 Buck-Boost Converter

The non-inverting buck-boost uses a four-switch topology. The simpler inverting buck-boost has

\[ V_{out} = -\frac{D}{1-D} V_{in} \]

The negative sign indicates the output polarity is inverted relative to the input. This is acceptable in many applications where only the magnitude of the regulated voltage matters.

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Chapter 12: Operational Amplifier Circuits and Applications

12.1 Ideal Op-Amp Analysis Techniques

The two golden rules of ideal op-amp analysis:

1. The voltage difference between the inverting and non-inverting inputs is zero: \(v_+ = v_-\) (virtual short).
2. No current flows into either input terminal: \(i_+ = i_- = 0\).

These rules apply whenever the op amp operates with negative feedback and within its linear range.

12.2 Precision Rectifiers

A simple diode rectifier introduces an error of \(\approx 0.6\) V (the diode threshold). The precision half-wave rectifier places the diode inside the feedback loop:

• When \(v_{in} > 0\): the op amp drives the diode forward, and the output follows the input exactly (\(v_o = v_{in}\)).
• When \(v_{in} < 0\): the diode blocks, the feedback is open, and the op amp saturates negatively, but \(v_o = 0\) V (the output node is disconnected from the saturated output).

The virtual ground at the summing junction ensures that the forward voltage drop of the diode appears across the op amp’s output — not across the load — giving precision rectification down to millivolt levels.

12.3 Logarithmic and Antilogarithmic Amplifiers

The exponential \(I\)–\(V\) characteristic of a BJT’s base-emitter junction is exploited to build log and antilog (exponential) amplifiers.

12.3.1 Log Amplifier

Place an NPN transistor in the feedback of an inverting amplifier, with the collector at the virtual ground (summing junction) and the emitter at the op-amp output:

\[ I_C = I_S e^{V_{BE}/V_T} = \frac{v_{in}}{R_1} \quad \Rightarrow \quad V_{BE} = V_T \ln\left(\frac{v_{in}}{R_1 I_S}\right) \]

The output voltage is \(v_o = -V_{BE}\):

\[ v_o = -V_T \ln\left(\frac{v_{in}}{R_1 I_S}\right) \]

This works for \(v_{in} > 0\) (PMOS transistor for negative inputs). The output is proportional to the natural log of the input.

12.3.2 Antilog Amplifier

Swapping the input resistor and transistor gives an antilog (exponential) amplifier:

\[ v_o = -R_1 I_S e^{v_{in}/V_T} \]

Log and antilog amplifiers combined enable analog multiplication and division, since \(\ln(a \cdot b) = \ln a + \ln b\).

12.4 Voltage-to-Current and Current-to-Voltage Converters

12.4.1 V-to-I Converter (Transconductance Amplifier)

A simple V-to-I converter for a floating load uses the series-series feedback topology:

\[ I_L = \frac{v_{in}}{R_S} \]

The load current is independent of the load impedance (for load within the compliance range), making this circuit a precision current source controlled by \(v_{in}\).

12.4.2 I-to-V Converter (Transimpedance Amplifier)

A transimpedance amplifier (TIA) converts input current to output voltage with gain \(R_f\):

\[ v_o = -i_{in} R_f \]

The virtual ground at the summing junction forces \(v_- = 0\), so the input sees zero impedance — ideal for photodiode current sensing.

12.5 Instrumentation Amplifiers

The three-op-amp instrumentation amplifier (INA) provides high differential gain with very high CMRR and high input impedance on both terminals:

\[ v_o = \left(1 + \frac{2R_1}{R_G}\right) \frac{R_3}{R_2} (v_2 - v_1) \]

The first stage uses two op amps in a non-inverting-like configuration that amplifies the differential signal while passing the common mode unchanged. The second stage is a differential amplifier that rejects the common mode. Gain is set by the single resistor \(R_G\), and CMRR is limited only by resistor matching.

12.6 Active Filters

Passive LC filters require bulky inductors and are difficult to integrate. Active RC filters using op amps and RC networks provide the same transfer functions with small, integrable components.

12.6.1 Sallen-Key Low-Pass Filter

The Sallen-Key topology is a second-order filter using a single op amp in unity-gain (or non-inverting gain) configuration:

\[ H(s) = \frac{K \omega_0^2}{s^2 + (\omega_0/Q) s + \omega_0^2} \]

For unity gain (\(K = 1\)) with components \(R_1 = R_2 = R\), \(C_1 = C_2 = C\):

\[ \omega_0 = \frac{1}{RC}, \quad Q = \frac{1}{2} \]

This gives a Butterworth response (\(Q = 1/\sqrt{2}\)) when \(C_1 = 2C_2\) and \(R_1 = R_2 = R\).

The transfer function derivation uses the virtual short: \(v_+ = v_- = v_o/K\) (for unity gain, \(v_+ = v_o\)). Writing KCL at each node and solving:

\[ H(s) = \frac{1}{1 + sC(R_1 + R_2) + s^2 C^2 R_1 R_2} \quad (K=1) \]

Comparing with the standard second-order form:

\[ \omega_0 = \frac{1}{C\sqrt{R_1 R_2}}, \quad Q = \frac{\sqrt{R_1 R_2}}{(R_1 + R_2) C} \]

12.6.2 Multiple-Feedback (MFB) Low-Pass Filter

The MFB topology uses the op amp in inverting mode with two feedback paths, providing an inverting second-order response. For equal resistors \(R_1 = R_3 = R\):

\[ H(s) = \frac{-1/(R^2 C_1 C_2)}{s^2 + s \frac{2}{R C_2} + \frac{1}{R^2 C_1 C_2}} \]

The MFB filter is preferred for low-\(Q\) applications because it requires fewer precision components.

12.6.3 State-Variable (KHN) Filter

The Kerwin-Huelsman-Newcomb (KHN) state-variable filter simultaneously provides low-pass, band-pass, and high-pass outputs from three op amps. The name derives from the state-variable representation of the second-order differential equation:

\[ \frac{d^2 v_{LP}}{dt^2} + \frac{\omega_0}{Q} \frac{d v_{LP}}{dt} + \omega_0^2 v_{LP} = \omega_0^2 v_{in} \]

Two integrators (op amps with capacitor feedback) and one summing amplifier implement this equation:

\[ H_{LP}(s) = \frac{\omega_0^2}{s^2 + (\omega_0/Q)s + \omega_0^2} \]\[ H_{BP}(s) = \frac{(\omega_0/Q) s}{s^2 + (\omega_0/Q)s + \omega_0^2} \]\[ H_{HP}(s) = \frac{s^2}{s^2 + (\omega_0/Q)s + \omega_0^2} \]

The state-variable filter allows independent adjustment of \(\omega_0\) (via the integrator RC) and \(Q\) (via the summing amplifier resistors), making it highly flexible. Adding the LP and HP outputs with the BP inverted gives a notch filter.

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Chapter 13: Oscillators

13.1 The Barkhausen Criterion

An oscillator is an amplifier with positive feedback at a specific frequency. For sustained oscillation, the loop gain must satisfy:

13.2 RC Phase-Shift Oscillator

Three identical RC sections in cascade, each providing 60° of phase shift at the oscillation frequency, provide the required 180° for an inverting amplifier. The oscillation frequency and gain condition are:

\[ \omega_0 = \frac{1}{RC\sqrt{6}}, \quad |A_v| \geq 29 \]

The minimum gain of 29 compensates for the attenuation of the RC ladder at \(\omega_0\). The circuit is simple but requires careful gain setting to avoid distortion.

13.3 Wien Bridge Oscillator

The Wien bridge oscillator uses a non-inverting amplifier with a band-pass RC network providing zero phase shift at \(\omega_0\). The RC network consists of a series RC and a parallel RC:

\[ \beta(j\omega) = \frac{j\omega RC}{1 - \omega^2 R^2 C^2 + 3j\omega RC} \]

At \(\omega_0 = 1/(RC)\), the phase of \(\beta = 0°\) and \(|\beta| = 1/3\). The amplifier must provide \(|A_v| = 3\):

\[ A_v = 1 + \frac{R_f}{R_1} = 3 \implies R_f = 2R_1 \]

Automatic gain control (AGC) — typically a lamp or JFET acting as a variable resistor — maintains \(R_f = 2R_1\) precisely, giving low-distortion sinusoidal output. The Wien bridge was famously used in Hewlett’s first product (HP 200A audio oscillator, 1939).

13.4 LC Oscillators

For high-frequency oscillation (RF range, MHz to GHz), LC tank circuits are used because RC oscillators have too high a noise floor and too much frequency drift.

13.4.1 Colpitts Oscillator

The Colpitts oscillator uses a capacitive voltage divider (\(C_1\), \(C_2\)) and an inductor \(L\). The tank circuit resonant frequency is

\[ \omega_0 = \frac{1}{\sqrt{L C_{eq}}}, \quad C_{eq} = \frac{C_1 C_2}{C_1 + C_2} \]

The feedback fraction is \(\beta = C_1/(C_1 + C_2)\), and oscillation starts when \(g_m > (C_1+C_2)^2/(L C_1^2 \omega_0^2 R)\) where \(R\) is the tank loss resistance.

13.4.2 Hartley Oscillator

The Hartley oscillator uses an inductive voltage divider (\(L_1\), \(L_2\)) and a capacitor \(C\). The equivalent inductance is \(L_{eq} = L_1 + L_2 + 2M\) where \(M\) is the mutual inductance. Hartley oscillators are mechanically tunable (variable capacitor) and are common in RF tuners.

13.5 Crystal Oscillators

A quartz crystal is an electromechanical resonator with an extremely high quality factor (\(Q > 10^4\), compared to \(Q \approx 100\) for LC tank circuits). Its equivalent circuit is a series RLC (\(R_s\), \(L_s\), \(C_s\)) in parallel with a case capacitance \(C_p\).

Two resonant frequencies exist:

• Series resonance: \(\omega_s = 1/\sqrt{L_s C_s}\)
• Parallel (anti)resonance: \(\omega_p = \omega_s \sqrt{1 + C_s/C_p} \approx \omega_s\left(1 + \frac{C_s}{2C_p}\right)\)

Between \(\omega_s\) and \(\omega_p\) (a range of tens of ppm), the crystal presents an inductive impedance and can replace the inductor in a Colpitts oscillator, giving very high frequency stability (0.001–10 ppm). Crystal oscillators are the frequency reference in virtually every digital system (microprocessors, PLLs, RF transceivers).

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Chapter 14: Waveform Generators

14.1 Schmitt Trigger

The Schmitt trigger is a comparator with hysteresis. An op amp with positive feedback (from output to non-inverting input) creates two distinct threshold voltages:

\[ V_{TH} = +V_{sat} \cdot \frac{R_1}{R_1 + R_2}, \quad V_{TL} = -V_{sat} \cdot \frac{R_1}{R_1 + R_2} \]

The hysteresis window is \(\Delta V = V_{TH} - V_{TL} = 2 V_{sat} R_1/(R_1+R_2)\). For \(v_{in} > V_{TH}\), the output snaps to \(-V_{sat}\); for \(v_{in} < V_{TL}\), it snaps to \(+V_{sat}\). This bistable behaviour eliminates chatter in threshold detection, filters noise at the switching point, and forms the basis of relaxation oscillators.

14.2 Astable Multivibrator

Connecting the Schmitt trigger output back to the inverting input through an RC network creates a self-sustaining square-wave oscillator. The capacitor charges and discharges between the two threshold voltages:

\[ T = 2 R C \ln\left(\frac{1 + R_1/R_2}{1 - R_1/R_2}\right) \]

For \(R_1 = R_2\): \(T = 2 RC \ln(3) \approx 2.197 RC\).

14.3 The 555 Timer

The 555 integrated circuit combines two comparators, an SR latch, a discharge transistor, and internal voltage divider to implement both monostable (one-shot) and astable (square-wave) timing functions.

14.3.1 Astable Configuration

With \(R_A\), \(R_B\), and \(C\):

\[ t_{high} = 0.693 (R_A + R_B) C, \quad t_{low} = 0.693 R_B C \]\[ f = \frac{1.443}{(R_A + 2R_B) C} \]

The duty cycle is \(D = (R_A + R_B)/(R_A + 2R_B) > 50\%\) in the basic configuration (the charging path always includes both \(R_A\) and \(R_B\)).

14.3.2 Monostable Configuration

Triggered by a negative edge at the trigger input, the output goes high for duration

\[ t_W = 1.1 R C \]

Applications include debouncing, pulse stretching, and one-shot timers.

14.4 Triangular Wave Generator

A triangular wave generator combines a Schmitt trigger with an integrator. The integrator ramps linearly between the two Schmitt trigger thresholds, creating a triangular wave at the integrator output and a square wave at the Schmitt trigger output:

\[ f_{tri} = \frac{R_2}{4 R_1 R_3 C} \]

where \(R_1\), \(R_2\) set the Schmitt trigger thresholds and \(R_3\), \(C\) are the integrator components. The amplitude of the triangular wave is

\[ V_{tri,peak} = V_{sat} \cdot \frac{R_1}{R_2} \]

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Chapter 15: Advanced Topics — Transistor-Level Op-Amp Design

15.1 The CMOS Two-Stage Op Amp — Full Analysis

The complete two-stage CMOS op amp integrates all the building blocks studied: differential pair first stage, active-load current mirror, CS second stage, and compensation. This section performs a full first-principles analysis.

15.1.1 Transistor Sizing and Bias

Given a tail current \(I_{SS}\), supply voltage \(V_{DD}\), and process parameters \((\mu_n C_{ox}, \mu_p C_{ox})\), the designer sizes the transistors to achieve:

1. Required transconductance \(g_{m1}\) (determines \(\omega_t\) via \(C_C\)).
2. Required output swing (sets overdrive voltages \(V_{OV}\)).
3. Adequate output resistance for gain (sets lengths \(L\)).

A typical design flow starts with \(g_{m1}\) from the GBW specification: given \(GBW = \omega_t / (2\pi)\) and a chosen \(C_C\):

\[ g_{m1} = 2\pi \cdot GBW \cdot C_C \]

Then \(I_{D1} = I_{SS}/2 = g_{m1}^2 / (2 \mu_p C_{ox} W_1/L_1)\) determines \(W_1/L_1\).

15.1.2 Common-Mode Input Range

The upper limit of the input common-mode voltage \(V_{icm,max}\) is set by the requirement that the tail current transistor remain in saturation:

\[ V_{icm,max} = V_{DD} - |V_{SG,M3}| - |V_{DS,Mtail,sat}| + V_{tn,M1,2} \]

The lower limit ensures the input pair remains in saturation:

\[ V_{icm,min} = -V_{SS} + V_{GS,M1,2} + V_{DS,Mtail,sat} \]

For rail-to-rail input, complementary input pairs (NMOS + PMOS differential pair in parallel) are used, each handling part of the common-mode range.

15.1.3 Systematic Offset Voltage

Process variations cause mismatch between nominally identical transistors. For the differential pair, mismatch in \(V_{tn}\) and \(W/L\) translates to an input-referred offset:

\[ V_{OS} \approx \Delta V_{tn} + \frac{V_{OV}}{2} \frac{\Delta(W/L)}{W/L} \]

where \(\Delta\) denotes the mismatch. Reducing \(V_{OS}\) requires increasing transistor area (larger \(W \cdot L\), which reduces \(\Delta(W/L)/(W/L)\)) — a fundamental area-accuracy trade-off.

15.2 Folded-Cascode Op Amp

The folded-cascode topology addresses the limited output swing of the telescopic cascode by “folding” the signal current from NMOS devices into PMOS cascode transistors (or vice versa). The output resistance is maintained at the cascode level:

\[ R_{out} \approx (g_{m2} r_{o2} r_{o1}) \| (g_{m4} r_{o4} r_{o3}) \]

while the minimum output voltage is reduced to approximately \(2 V_{OV}\) instead of \(4 V_{OV}\) for the telescopic cascode.

The folded-cascode op amp is a single-stage op amp (no second gain stage), and its output is taken directly at the high-resistance node. It requires a large load capacitance to set the dominant pole at the output node — which is naturally provided by the compensation capacitor.

The unity-gain frequency is

\[ \omega_t \approx \frac{g_{m1}}{C_L} \]

and stability requires that all other poles be above \(\omega_t\).