These notes synthesize the standard graduate-accessible treatment of electronic devices, drawing on the course topic schedule for ECE 331 (University of Waterloo, Winter 2025) and the canonical references listed at the end. They are designed to be rigorous and self-contained, suitable for students who have completed a first course in semiconductor physics (ECE 231 or equivalent) and are ready for device-level derivations. The treatment parallels Neamen Chapters 6–11 and 14, supplemented by fabrication material from Jaeger and Plummer–Deal–Griffin.

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Sources and References

The following publicly available references form the scholarly foundation of these notes.

• D. A. Neamen, Semiconductor Physics and Devices: Basic Principles, 4th ed. McGraw-Hill, 2012. (Primary textbook; Chapters 6–11, 14.)
• R. C. Jaeger, Introduction to Microelectronic Fabrication, 2nd ed. (Modular Series on Solid State Devices, Vol. 5). Prentice Hall, 2002. (Fabrication chapters.)
• J. D. Plummer, M. D. Deal, and P. B. Griffin, Silicon VLSI Technology: Fundamentals, Practice and Modeling. Prentice Hall, 2000. Available free online at plummer.stanford.edu.
• S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, 3rd ed. Wiley-Interscience, 2007.
• R. F. Pierret, Semiconductor Device Fundamentals. Addison-Wesley, 1996.
• MIT OpenCourseWare 6.012, Microelectronic Devices and Circuits, open lecture notes and problem sets. ocw.mit.edu.
• M. Lundstrom and C. Jeong, Nanoscale Transistors: Device Physics, Modeling and Simulation. Springer, 2006. Lecture series also available at nanohub.org.

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Chapter 1: Semiconductor Foundations — Non-Equilibrium Carriers

1.1 Thermal Equilibrium and the Mass-Action Law

A semiconductor in thermal equilibrium is a closed system at constant temperature with no net external energy input. In this state two key conditions hold simultaneously. First, the product of carrier concentrations satisfies the mass-action law:

\[ n_0 p_0 = n_i^2 \]

where \(n_i\) is the intrinsic carrier concentration. This result follows from the detailed balance principle applied to band-to-band generation and recombination, and is independent of doping. The intrinsic concentration itself is strongly temperature-dependent:

\[ n_i^2 = N_c N_v \exp\!\left(-\frac{E_g}{k_B T}\right) \]

The effective densities of states are \(N_c = 2(2\pi m_{de}^* k_B T / h^2)^{3/2}\) and \(N_v = 2(2\pi m_{dh}^* k_B T / h^2)^{3/2}\), where \(m_{de}^*\) and \(m_{dh}^*\) are the density-of-states effective masses. For silicon at 300 K: \(n_i \approx 1.5\times10^{10}\;\text{cm}^{-3}\), \(N_c \approx 2.86\times10^{19}\;\text{cm}^{-3}\), \(N_v \approx 3.10\times10^{19}\;\text{cm}^{-3}\), \(E_g = 1.12\;\text{eV}\).

Second, charge neutrality holds throughout a uniformly doped region:

\[ n_0 + N_A^- = p_0 + N_D^+ \]

At room temperature with complete ionization (\(N_A^- \approx N_A\), \(N_D^+ \approx N_D\)), combined with the mass-action law, the equilibrium concentrations in an n-type sample (\(N_D \gg N_A\)) are:

\[ n_0 \approx \frac{(N_D - N_A) + \sqrt{(N_D - N_A)^2 + 4n_i^2}}{2} \approx N_D - N_A \]\[ p_0 = \frac{n_i^2}{n_0} \approx \frac{n_i^2}{N_D - N_A} \]

The Fermi level position follows from the Boltzmann approximation:

\[ E_F - E_i = k_BT \ln\!\left(\frac{n_0}{n_i}\right) = k_BT \ln\!\left(\frac{N_D}{n_i}\right) \]

1.2 Non-Equilibrium: Excess Carriers and Quasi-Fermi Levels

When a device is illuminated, forward-biased, or subjected to particle bombardment, carriers depart from their equilibrium values:

\[ n = n_0 + \delta n, \qquad p = p_0 + \delta p \]

The deviations \(\delta n\) and \(\delta p\) are the excess carrier concentrations. For band-to-band generation (optical generation, impact ionization), pairs are created together so that \(\delta n = \delta p\) throughout any charge-neutral region.

The current density driven by a gradient in quasi-Fermi level is the most compact statement of transport:

\[ J_n = \mu_n n \frac{d F_n}{dx}, \qquad J_p = -\mu_p p \frac{d F_p}{dx} \]

This form, valid for both drift and diffusion in an arbitrary band structure, unifies the two separate drift and diffusion terms into a single expression. In a region of uniform composition at equilibrium, both gradients vanish and both currents are zero by construction — a consistency check.

1.3 Recombination Mechanisms

1.3.1 Band-to-Band (Radiative) Recombination

In direct-gap semiconductors (GaAs, InP), electrons in the conduction band recombine directly with holes in the valence band, emitting a photon. The net recombination rate is:

\[ U_{rad} = B_r (np - n_i^2) \]

where \(B_r\) is the bimolecular recombination coefficient. For GaAs, \(B_r \approx 10^{-10}\;\text{cm}^3/\text{s}\). For indirect-gap silicon, \(B_r \approx 10^{-15}\;\text{cm}^3/\text{s}\), making band-to-band recombination negligible compared to SRH.

1.3.2 Shockley–Read–Hall Recombination

The dominant recombination mechanism in indirect-gap semiconductors is Shockley–Read–Hall (SRH) recombination via trap states at energy \(E_t\) within the bandgap, introduced by impurities or crystal defects. Carrier capture and emission at the trap involve four processes: electron capture, electron emission, hole capture, hole emission. In steady state, the rates must balance and the net recombination rate is:

\[ U_{SRH} = \frac{\sigma_n \sigma_p v_{th} N_t (np - n_i^2)}{\sigma_n(n + n_1) + \sigma_p(p + p_1)} \]

where \(\sigma_n, \sigma_p\) are electron and hole capture cross sections, \(v_{th}\) is the thermal velocity, \(N_t\) is the trap density, and

\[ n_1 = n_i \exp\!\left(\frac{E_t - E_i}{k_BT}\right), \qquad p_1 = n_i \exp\!\left(\frac{E_i - E_t}{k_BT}\right) \]

Define minority carrier lifetimes \(\tau_n = (\sigma_n v_{th} N_t)^{-1}\) and \(\tau_p = (\sigma_p v_{th} N_t)^{-1}\). Then:

\[ U_{SRH} = \frac{np - n_i^2}{\tau_p (n + n_1) + \tau_n (p + p_1)} \]

Traps at mid-gap (\(E_t = E_i\), so \(n_1 = p_1 = n_i\)) are the most efficient recombination centres because they maximise the denominator’s numerator balance. Under low-level injection into p-type material (\(\delta n \ll p_0\), so \(n + n_1 \approx n_0 + n_1\), \(p + p_1 \approx p_0 \gg n_1\)):

\[ U_{SRH} \approx \frac{\delta n}{\tau_n} \]

This is the familiar first-order recombination. The minority carrier lifetime \(\tau_n\) is the dominant material parameter that determines how quickly injected carriers recombine.

1.3.3 Auger Recombination

At very high carrier densities (degenerate doping or intense injection), a third carrier can carry away the recombination energy, giving the Auger mechanism with rate:

\[ U_{Auger} = (C_n n + C_p p)(np - n_i^2) \]

where \(C_n, C_p \approx 10^{-30}\;\text{cm}^6/\text{s}\) in silicon. Auger is proportional to \(n^3\) for heavy n-type doping, and limits the minority carrier lifetime in emitters of BJTs with \(N_E > 10^{18}\;\text{cm}^{-3}\). It also sets the fundamental efficiency limit in solar cells.

1.4 Minority Carrier Diffusion Equation

The continuity equation for electrons in a p-type semiconductor, combined with Fick’s law and the generation-recombination rate, gives the minority carrier diffusion equation:

\[ D_n \frac{\partial^2(\delta n)}{\partial x^2} - \frac{\delta n}{\tau_n} + G_L = \frac{\partial(\delta n)}{\partial t} \]

In steady state with no external generation the homogeneous solution is:

\[ \delta n(x) = A e^{-x/L_n} + B e^{x/L_n} \]

where \(L_n = \sqrt{D_n \tau_n}\) is the electron diffusion length. For silicon with \(D_n = 25\;\text{cm}^2/\text{s}\) and \(\tau_n = 10^{-6}\;\text{s}\): \(L_n = \sqrt{25 \times 10^{-6}} \approx 50\;\mu\text{m}\). Carriers injected at a surface (\(x=0\)) decay exponentially over this length scale, defining the physical extent of minority-carrier dominated current flow in the quasi-neutral region.

The Einstein relations connect mobility and diffusivity through thermodynamics:

\[ \frac{D_n}{\mu_n} = \frac{D_p}{\mu_p} = V_T = \frac{k_BT}{q} \approx 25.85\;\text{mV at 300 K} \]

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Chapter 2: The pn Junction — Advanced Analysis

2.1 Depletion Approximation and Electrostatics

At an abrupt pn junction in equilibrium, the built-in potential across the depletion region is:

\[ V_{bi} = V_T \ln\!\left(\frac{N_A N_D}{n_i^2}\right) \]

This follows from the requirement that \(E_F\) is spatially constant. Within the depletion approximation (complete ionization, zero carrier density in the depletion region), Poisson’s equation gives:

\[ \frac{d^2\psi}{dx^2} = -\frac{\rho}{\varepsilon_s} = \begin{cases} qN_D/\varepsilon_s & 0 < x < x_n \\ -qN_A/\varepsilon_s & -x_p < x < 0 \end{cases} \]

Integrating once gives the triangular electric field profile with peak at the metallurgical junction:

\[ |\mathcal{E}_{max}| = \frac{qN_D x_n}{\varepsilon_s} = \frac{qN_A x_p}{\varepsilon_s} \]

Charge neutrality (\(N_D x_n = N_A x_p\)) determines the fractional penetration into each side. Integrating again, the total depletion width under applied voltage \(V\) is:

\[ W = x_n + x_p = \sqrt{\frac{2\varepsilon_s(V_{bi}-V)}{q}\left(\frac{1}{N_A} + \frac{1}{N_D}\right)} \]

The junction capacitance per unit area is that of a parallel-plate capacitor with plate separation \(W\):

\[ C_j = \frac{\varepsilon_s}{W} = \sqrt{\frac{q\varepsilon_s}{2(V_{bi}-V)}\cdot\frac{N_A N_D}{N_A + N_D}} \]

The Mott–Schottky representation linearises this as \(1/C_j^2 = [2(V_{bi}-V)/(q\varepsilon_s)] \cdot (N_A^{-1}+N_D^{-1})\), useful for extracting doping and built-in voltage from C-V measurements.

2.2 Non-Uniformly Doped (Graded) Junctions

Most practical junctions formed by diffusion have a linearly graded profile near the metallurgical junction, characterised by the impurity gradient \(a\) (\(\text{cm}^{-4}\)). Within the depletion region, \(\rho = qax\). Poisson’s equation then gives a quadratic electric field:

\[ \mathcal{E}(x) = -\frac{qa}{2\varepsilon_s}\left[\left(\frac{W}{2}\right)^2 - x^2\right] \]

The potential drop and depletion width are related by:

\[ V_{bi} = \frac{qa W^3}{12\varepsilon_s}, \qquad W = \left(\frac{12\varepsilon_s V_{bi}}{qa}\right)^{1/3} \]

The capacitance follows:

\[ C_j = \frac{\varepsilon_s}{W} = \left(\frac{q a \varepsilon_s^2}{12(V_{bi}-V)}\right)^{1/3} \]

Note the \((V_{bi}-V)^{-1/3}\) dependence, distinct from the abrupt-junction \((V_{bi}-V)^{-1/2}\). On a log–log Mott–Schottky plot, the slope of \(\log C_j\) vs. \(\log(V_{bi}-V)\) reveals the junction grading: −1/3 for linear, −1/2 for abrupt.

2.3 Ideal Diode Equation — Detailed Derivation

With the junction under forward bias \(V\), the law of the junction sets the minority carrier concentrations at the depletion region edges. For holes injected into the n-side:

\[ p_n(x_n) = p_{n0} \exp\!\left(\frac{V}{V_T}\right) \equiv p_{n0} e^{V/V_T} \]

Solving the minority hole diffusion equation in the n-side with boundary condition \(p_n \to p_{n0}\) as \(x \to \infty\):

\[ \delta p_n(x) = p_{n0}\left(e^{V/V_T}-1\right) e^{-(x-x_n)/L_p} \]

The hole current at \(x = x_n\) is:

\[ J_p = -qD_p \frac{d(\delta p_n)}{dx}\bigg|_{x_n} = \frac{qD_p p_{n0}}{L_p}\left(e^{V/V_T}-1\right) \]

By symmetry, the electron current contribution from the p-side at \(x = -x_p\) is \(qD_n n_{p0}/L_n \cdot (e^{V/V_T}-1)\). The total diode current density (neglecting recombination in the depletion region) is:

\[ J = J_0 \left(e^{V/V_T} - 1\right) \]\[ J_0 = \frac{qD_p p_{n0}}{L_p} + \frac{qD_n n_{p0}}{L_n} = qn_i^2\left(\frac{D_p}{L_p N_D} + \frac{D_n}{L_n N_A}\right) \]

The second equality uses \(p_{n0} = n_i^2/N_D\) and \(n_{p0} = n_i^2/N_A\). This is the Shockley ideal diode equation.

Deviations from ideality. The measured \(I\)-\(V\) characteristic deviates from the ideal because:

1. Depletion region recombination adds a current component with ideality factor \(n=2\) at low forward bias (SRH recombination in the depletion region, where \(n \approx p \approx n_i\), giving \(U \approx n_i/\tau\)).
2. Series resistance at high forward current: the voltage across the junction is \(V - IR_s\), causing the slope on a semilog plot to decrease.
3. High-level injection: when \(\delta p \sim N_D\), the simple expression breaks down.

The two-diode model captures the first two effects:

\[ I = I_{s1} e^{V/V_T} + I_{s2} e^{V/(2V_T)} \]

2.4 Junction Breakdown Mechanisms

2.4.1 Zener (Band-to-Band Tunneling) Breakdown

In heavily doped, narrow junctions, the depletion width is so thin (\(W < 10\;\text{nm}\)) that electrons tunnel quantum-mechanically across the forbidden gap — from the valence band on the p-side directly to conduction band states on the n-side. This is band-to-band tunneling (BTBT) or Zener tunneling.

The WKB approximation gives the tunneling transmission coefficient through a triangular barrier (valid for the triangular potential well produced by the junction field \(\mathcal{E}\)):

\[ T_{WKB} \approx \exp\!\left(-\frac{4\sqrt{2m_r^*}\,E_g^{3/2}}{3q\hbar|\mathcal{E}|}\right) \]

where \(m_r^* = m_e^* m_h^*/(m_e^* + m_h^*)\) is the reduced mass. The tunnel current density is roughly:

\[ J_{BTBT} \approx \frac{q^2 \mathcal{E} \sqrt{m_r^*}}{4\pi^2 \hbar^2 \sqrt{E_g}} T_{WKB} \cdot V_{applied} \]

Because \(E_g\) decreases with temperature (for silicon, \(E_g(T) \approx 1.17 - 4.73\times10^{-4}T^2/(T+636)\;\text{eV}\)), the Zener current increases with temperature at fixed bias — a negative temperature coefficient of breakdown voltage.

2.4.2 Avalanche Breakdown

For more lightly doped junctions with larger depletion widths, impact ionization is the dominant breakdown mechanism. A carrier traversing the high-field region can generate an electron-hole pair if its kinetic energy exceeds a threshold \(E_{th} > E_g\) (the excess is required to conserve momentum). Each new carrier can in turn generate further pairs — a self-sustaining chain reaction.

The ionization rates \(\alpha_n(\mathcal{E})\) and \(\alpha_p(\mathcal{E})\) are fitted empirically to:

\[ \alpha_{n,p} = A_{n,p} \exp\!\left(-\frac{B_{n,p}}{|\mathcal{E}|}\right) \]

For silicon at room temperature: \(A_n \approx 7.0\times10^5\;\text{cm}^{-1}\), \(B_n \approx 1.23\times10^6\;\text{V/cm}\). The avalanche multiplication factor for electron injection at the p-edge is:

\[ M_n = \frac{1}{1 - \int_0^W \alpha_n \exp\!\left[-\int_0^x (\alpha_n - \alpha_p)dx'\right]dx} \]

For the simplified case \(\alpha_n = \alpha_p = \alpha\) (approximately valid for silicon in the 1–10 V range), this reduces to:

\[ M = \frac{1}{1 - \int_0^W \alpha\,dx} \]

Breakdown is defined as \(M \to \infty\), i.e., the Townsend criterion \(\int_0^W \alpha\,dx = 1\). Empirically, the breakdown voltage of a one-sided abrupt junction scales as:

\[ BV \approx \frac{\varepsilon_s \mathcal{E}_{crit}^2}{2qN_B} \]

where \(N_B\) is the lighter background doping. Using \(\mathcal{E}_{crit} \approx 3\times10^5\;\text{V/cm}\) for silicon and \(\varepsilon_s = 11.7\varepsilon_0\), a sample calculation: for \(N_B = 10^{15}\;\text{cm}^{-3}\), \(BV \approx 290\;\text{V}\).

Avalanche breakdown carries a positive temperature coefficient because increased phonon scattering at higher temperatures shortens the carrier mean free path, requiring a larger applied field (hence higher voltage) to ionize. Conversely, lower temperature allows avalanche at lower voltage.

2.5 Charge Storage and Reverse Recovery

Under forward bias, minority carriers accumulate in the quasi-neutral regions. The stored charge in the p-side (minority holes in n-side, for the long-diode model) is:

\[ Q_p = \int_0^\infty q \delta p_n(x)\,dx = qL_p p_{n0}(e^{V/V_T}-1) = I_p \tau_p \]

where the last equality uses \(I_p = qAD_p\delta p_n/L_p\) and \(L_p = D_p\tau_p/L_p\). Thus \(Q = I\tau\) in general, where \(\tau\) is the effective minority carrier lifetime.

Reverse recovery transient. When the diode switches from forward current \(I_F\) to a reverse supply through resistance \(R\), two phases occur:

1. Storage phase (duration \(t_s\)): The junction remains forward-biased because stored minority charge maintains the excess concentration boundary condition. Reverse current flows at approximately \(I_R \approx (V_{rr} + V_F)/R\). The charge decays under the combined effects of extraction and recombination.

2. Recovery phase (duration \(t_{rr} - t_s\)): Once the stored charge is exhausted, the junction depletes and the current decays exponentially toward zero with time constant \(\tau\).

The total reverse recovery time \(t_{rr}\) is a key figure of merit: \(t_{rr} \propto \sqrt{\tau}\) for many practical cases. Switching diodes use ion implantation of gold or platinum to introduce mid-gap traps, reducing \(\tau\) from microseconds to nanoseconds at the cost of slightly higher forward voltage.

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Chapter 3: Metal–Semiconductor Junctions

3.1 Schottky Barrier Formation and Band Alignment

When a metal contacts an n-type semiconductor, charge transfer occurs until the Fermi levels align. In the Schottky–Mott ideal model, the barrier height is set by the difference of work functions:

\[ \phi_B = \phi_m - \chi_s \]

where \(\phi_m\) is the metal work function and \(\chi_s\) is the semiconductor electron affinity (measured from the vacuum level to the conduction band minimum). The built-in potential is then:

\[ V_{bi} = \phi_B - \phi_n = (\phi_m - \chi_s) - V_T\ln(N_c/N_D) \]

In practice, a high density of interface states (typically \(\sim 10^{12}–10^{13}\;\text{cm}^{-2}\text{eV}^{-1}\) in silicon) pins the surface Fermi level near a charge neutrality level \(E_{CNL}\) that lies \(\sim 0.3\;\text{eV}\) above the valence band in silicon. The effective barrier height is a weighted average:

\[ \phi_B = S(\phi_m - \chi_s) + (1-S)(E_g - E_{CNL})/q \]

where \(S \in [0,1]\) is the slope parameter. For silicon, \(S \approx 0.27\), indicating strong pinning — \(\phi_B\) changes only about 0.27 eV per eV change in \(\phi_m\).

3.2 Thermionic Emission Theory

The dominant current mechanism in Schottky diodes at room temperature is thermionic emission: carriers in the metal (or semiconductor) thermally excited over the barrier rather than the diffusion mechanism. The current density from semiconductor to metal is proportional to the number of electrons with enough energy to surmount \(\phi_B\):

\[ J_{s\to m} = A^{**} T^2 \exp\!\left(-\frac{q\phi_B}{k_BT}\right)\exp\!\left(\frac{qV}{k_BT}\right) \]

The return current (metal to semiconductor) is:

\[ J_{m\to s} = A^{**} T^2 \exp\!\left(-\frac{q\phi_B}{k_BT}\right) \]

The net forward current is:

\[ J = J_s\left[e^{qV/k_BT} - 1\right], \qquad J_s = A^{**}T^2 e^{-q\phi_B/k_BT} \]

where \(A^{**} = 4\pi q m^* k_B^2/h^3\) is the effective Richardson constant (including quantum-mechanical reflection effects). For n-type silicon, \(A^{**} \approx 110\;\text{A cm}^{-2}\text{K}^{-2}\).

The Schottky diode’s saturation current \(J_s\) is typically 6–8 orders of magnitude larger than a comparable pn junction’s \(I_s\), because the barrier height (0.6–0.8 eV) is much less than \(E_g\) (1.12 eV). This gives the Schottky diode a much lower turn-on voltage (~0.3 V vs. ~0.7 V for silicon pn junctions).

3.2.1 Image Force Lowering

The potential energy of an electron near the metal surface is modified by the attraction to its image charge in the metal and by the external field:

\[ V(x) = -\frac{q}{16\pi\varepsilon_s x} - q\mathcal{E}_{max}x + \phi_B \]

The maximum of \(V(x)\) is found at \(x_m = \sqrt{q/(16\pi\varepsilon_s |\mathcal{E}_{max}|)}\), giving an effective barrier reduction:

\[ \Delta\phi_B = \sqrt{\frac{q|\mathcal{E}_{max}|}{4\pi\varepsilon_s}} \]

For a field of \(10^5\;\text{V/cm}\) in silicon: \(\Delta\phi_B \approx 15\;\text{mV}\). While small at low bias, under high reverse fields \(|\mathcal{E}_{max}|\) grows and the effective barrier decreases, causing the reverse current to increase with reverse voltage — the soft reverse I-V characteristic of Schottky diodes.

3.3 Ohmic Contacts — Design and Physics

An ohmic contact must pass current in both directions with negligible voltage drop compared to the device voltage. Two engineering approaches:

Accumulation contact. If \(\phi_m < \phi_s\) for n-type, electrons accumulate at the surface rather than depleting, and no barrier forms. In practice this requires choosing metals with very low work function (e.g., n-type ohmic contacts in GaN use Ti/Al stacks), and the situation is complicated by Fermi level pinning.

Tunneling ohmic contact. For degenerate doping (\(N_D > 10^{19}\;\text{cm}^{-3}\)), the depletion width \(W \propto 1/\sqrt{N_D}\) is so narrow that carriers tunnel efficiently through the barrier regardless of \(\phi_B\). The specific contact resistance is:

\[ \rho_c \propto \exp\!\left(\frac{2\phi_B\sqrt{\varepsilon_s m^*}}{\hbar\sqrt{N_D}}\right) \]

This decreases exponentially with \(\sqrt{N_D}\), motivating the use of heavily doped contact regions. For silicon, typical \(\rho_c \sim 10^{-7}\;\Omega\text{cm}^2\) at \(N_D = 10^{20}\;\text{cm}^{-3}\). The contact resistance for a contact area \(A_c\) is \(R_c = \rho_c/A_c\), and for a contact of radius \(r_c\) it is \(R_c = \rho_c/(2\pi r_c L_T)\) where \(L_T = \sqrt{\rho_c/R_{sh}}\) is the transfer length and \(R_{sh}\) is the sheet resistance of the contacted layer.

In modern CMOS, all source/drain contacts use a self-aligned silicide (salicide): after gate patterning and S/D implant, a metal (Ni, Co, or Ti) is deposited, annealed to form the silicide (NiSi, CoSi\(_2\), or TiSi\(_2\)) at all exposed silicon surfaces, and then the unreacted metal is stripped. The silicide reduces sheet resistance from \(\sim 100\;\Omega/\square\) (poly or diffusion) to \(\sim 3–10\;\Omega/\square\), dramatically reducing contact and sheet resistance.

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Chapter 4: MOS Capacitor and MOSFET Threshold Voltage

4.1 Ideal MOS Capacitor — Band Diagrams

The MOS capacitor is the heart of the MOSFET. Consider a metal gate / SiO\(_2\) / p-Si structure. The surface potential \(\psi_s\) is defined as the potential at the Si surface relative to the bulk:

The threshold condition is \(\psi_s = 2\phi_F\), at which the surface electron concentration equals the bulk hole concentration: \(n_s = N_A\). This is the onset of strong inversion.

4.2 Real MOS Capacitor — Fixed and Interface Charges

Four types of charges complicate the ideal picture:

1. Fixed oxide charge \(Q_{f}\): positive charge at the Si/SiO\(_2\) interface (due to broken bonds during oxidation). For (100) Si/dry-oxide: \(Q_f/q \approx 10^{10}–10^{11}\;\text{cm}^{-2}\).
2. Interface trapped charge \(Q_{it}\): energy-distributed traps throughout the bandgap at the interface. These charge/discharge as the Fermi level moves through the gap, causing frequency dispersion in C-V and degradation of subthreshold slope.
3. Mobile ionic charge \(Q_m\): Na\(^+\), K\(^+\) ions that drift under field/temperature. Controlled by clean-room procedures.
4. Oxide trapped charge \(Q_{ot}\): trapped electrons or holes throughout the bulk of the oxide, generated by radiation or hot-carrier injection.

The flat-band voltage shift from these charges:

\[ V_{FB} = \phi_{ms} - \frac{1}{C_{ox}}\left[Q_f + Q_{it}(E_F) + Q_m + Q_{ot}\right] \]

where \(\phi_{ms}\) is the metal-silicon work function difference. For n\(^+\) poly gate on p-type Si: \(\phi_{ms} \approx -1.1\;\text{V}\).

4.3 Threshold Voltage — Complete Expression

At \(\psi_s = 2\phi_F\), the maximum depletion width is:

\[ x_{dmax} = \sqrt{\frac{4\varepsilon_s\phi_F}{qN_A}} \]

For silicon with \(N_A = 10^{16}\;\text{cm}^{-3}\): \(\phi_F = 0.026\ln(10^{16}/1.5\times10^{10}) \approx 0.347\;\text{V}\), \(x_{dmax} = \sqrt{4\times11.7\times8.85\times10^{-14}\times0.347/(1.6\times10^{-19}\times10^{16})} \approx 300\;\text{nm}\).

The depletion charge: \(Q_{dep} = -qN_A x_{dmax}\). The threshold voltage:

\[ V_T = V_{FB} + 2\phi_F - \frac{Q_{dep}}{C_{ox}} = V_{FB} + 2\phi_F + \frac{\sqrt{4q\varepsilon_s N_A \phi_F}}{C_{ox}} \]

Defining the body effect coefficient:

\[ \gamma = \frac{\sqrt{2q\varepsilon_s N_A}}{C_{ox}} \]

we can write \(V_T = V_{FB} + 2\phi_F + \gamma\sqrt{2\phi_F}\), and more generally, with a reverse body bias \(V_{SB} > 0\):

\[ V_T(V_{SB}) = V_{T0} + \gamma\left(\sqrt{2\phi_F + V_{SB}} - \sqrt{2\phi_F}\right) \]

This is the body effect (back-gate effect or substrate bias effect). It is critical in circuits where the source is not tied to the body (e.g., stacked NMOS in a NAND gate), raising \(V_T\) of upper transistors.

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Chapter 5: MOSFET I–V Characteristics and Small-Signal Model

5.1 Gradual Channel Approximation

In the gradual channel approximation, the device is sliced into differential resistances along the channel. At position \(x\) with local channel potential \(V(x)\) (measured from source, so \(V(0)=0\), \(V(L)=V_{DS}\)), the inversion charge per unit area is:

\[ Q_n(x) = -C_{ox}[V_{GS} - V_T - V(x)] \]

This is positive when \(V_{GS} - V_T > V(x)\) (channel not pinched off). The drift current is:

\[ I_D = -W\mu_n Q_n \frac{dV}{dx} = W\mu_n C_{ox}[V_{GS}-V_T-V(x)]\frac{dV}{dx} \]

Since \(I_D\) is constant along the channel (steady state), integrate both sides from \(x=0\) to \(x=L\):

\[ I_D \int_0^L dx = W\mu_n C_{ox}\int_0^{V_{DS}}[V_{GS}-V_T-V]\,dV \]\[ I_D = \frac{W\mu_n C_{ox}}{L}\left[(V_{GS}-V_T)V_{DS} - \frac{V_{DS}^2}{2}\right] \quad \text{linear region} \]

Maximising \(I_D\) over \(V_{DS}\) gives the saturation onset at \(V_{DS,sat} = V_{GS}-V_T\) with:

\[ I_{D,sat} = \frac{W\mu_n C_{ox}}{2L}(V_{GS}-V_T)^2 \]

The transconductance in saturation:

\[ g_m = \frac{\partial I_D}{\partial V_{GS}}\bigg|_{sat} = \frac{W\mu_n C_{ox}}{L}(V_{GS}-V_T) = \sqrt{2I_D \cdot \frac{W\mu_n C_{ox}}{L}} \]

The second form is useful: \(g_m \propto \sqrt{I_D}\) for a fixed W/L, unlike the BJT where \(g_m = I_C/V_T \propto I_C\).

5.2 Small-Signal Equivalent Circuit

Around a quiescent operating point in saturation, the MOSFET is characterised by:

• Transconductance: \(g_m = \partial I_D/\partial V_{GS}\)
• Output conductance: \(g_{ds} = \partial I_D/\partial V_{DS} = \lambda I_D\) (from channel length modulation)
• Body transconductance: \(g_{mb} = \partial I_D/\partial V_{BS} = g_m\gamma/(2\sqrt{2\phi_F+V_{SB}})\)

At high frequency, capacitances are added:

• \(C_{gs} = \frac{2}{3}WLC_{ox} + WC_{ov,s}\): gate-to-source
• \(C_{gd} = WC_{ov,d}\): gate-to-drain (overlap only in saturation)
• \(C_{sb}, C_{db}\): source and drain junction capacitances

The Miller effect multiplies \(C_{gd}\) by \((1 + g_m R_L)\) when referred to the input, making it the dominant bandwidth-limiting capacitance in inverting amplifiers.

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Chapter 6: Non-Ideal MOSFET Effects

6.1 Short-Channel Effects and Threshold Voltage Roll-Off

As the channel length \(L\) approaches the depletion widths of the source and drain junctions, two-dimensional charge-sharing effects become important. In a long-channel device, essentially all the depletion charge under the gate is induced by the gate field. In a short-channel device, the source and drain junctions each contribute a depletion region that shares control of a fraction of the channel charge. The gate needs to induce less charge to achieve inversion, so \(V_T\) decreases with decreasing \(L\).

A trapezoidal charge-sharing model gives:

\[ \Delta V_T \approx -\frac{qN_A x_{dmax}}{C_{ox}} \cdot \frac{x_j}{L}\left(\sqrt{1 + \frac{2W_{SD}}{x_j}} - 1\right) \]

where \(x_j\) is the junction depth and \(W_{SD} = x_{dmax}\) is the junction depletion width. This negative \(\Delta V_T\) increases in magnitude as \(L\) decreases — the device turns on more easily and off-state leakage increases. The solution is: (1) shallower junctions (\(x_j \ll L\)), (2) higher channel doping (\(x_{dmax}\) smaller), (3) thinner gate oxide (\(C_{ox}\) larger, suppresses the pre-factor), and ultimately (4) multiple-gate structures (FinFET, GAA).

6.2 Drain-Induced Barrier Lowering (DIBL)

Even holding \(L\) constant, increasing \(V_{DS}\) expands the drain depletion region into the channel, lowering the source-to-channel potential barrier and thus reducing \(V_T\). The DIBL coefficient:

\[ \text{DIBL} = -\frac{\Delta V_T}{\Delta V_{DS}} \quad [\text{mV/V}] \]

is typically 50–150 mV/V for well-designed devices at the 45 nm node, rising to several hundred mV/V in poorly controlled short-channel devices. DIBL degrades the subthreshold swing (the off-state current increases faster with \(V_{DS}\)) and is particularly damaging in logic circuits where \(V_{DS}\) fluctuates.

6.3 Velocity Saturation and the Short-Channel I–V Model

The piecewise linear velocity–field model captures the transition between ohmic and saturated transport:

\[ v(x) = \frac{\mu_{eff}\mathcal{E}(x)}{1 + \mathcal{E}(x)/\mathcal{E}_{sat}} \]

where \(\mathcal{E}_{sat} = v_{sat}/\mu_{eff}\) is the saturation field. Incorporating this into the channel current integral:

\[ I_D = \frac{W\mu_{eff}C_{ox}}{1 + V_{DS}/(v_{sat}L)}\left[(V_{GS}-V_T)V_{DS} - \frac{V_{DS}^2}{2}\right] \]

Saturation now occurs when the numerator is maximised subject to the velocity constraint. The saturation voltage is:

\[ V_{DS,sat} = \frac{(V_{GS}-V_T)\mathcal{E}_{sat}L}{(V_{GS}-V_T) + \mathcal{E}_{sat}L} \]

For long channel (\(\mathcal{E}_{sat}L \gg V_{GS}-V_T\)): \(V_{DS,sat} \to V_{GS}-V_T\) (classical pinch-off). For short channel (\(\mathcal{E}_{sat}L \ll V_{GS}-V_T\)): \(V_{DS,sat} \to \mathcal{E}_{sat}L = v_{sat}L/\mu\), and the saturation current is:

\[ I_{D,sat} \approx WC_{ox}(V_{GS}-V_T)v_{sat} \]

Linear in \((V_{GS}-V_T)\) and independent of \(L\). This fundamental change in the \(I_D\)–\(V_{GS}\) relationship is the hallmark of short-channel, velocity-saturated devices, and it limits the benefit of further shrinking \(L\).

6.4 Hot-Carrier Effects and LDD

At high lateral fields near the drain, carriers gain kinetic energy well above thermal equilibrium. The distribution function develops a hot tail. The substrate current generated by impact ionization near the drain:

\[ I_{sub} \approx C_1 (V_{DS} - V_{DS,sat}) I_D \exp\!\left(-\frac{C_2}{V_{DS}-V_{DS,sat}}\right) \]

where \(C_1, C_2\) are empirical constants related to the ionization coefficients. \(I_{sub}\) peaks at \(V_{DS} \approx 1.5(V_{GS}-V_T)\) and is the standard diagnostic used to measure peak oxide-field damage rate.

Hot-carrier-induced degradation involves:

1. Interface trap creation: hot carriers break Si–H bonds at the Si/SiO\(_2\) interface, creating \(D_{it}\). This increases \(|V_T|\) and decreases \(g_m\) (electron channel mobility falls due to additional Coulomb and interface scattering).
2. Oxide charge trapping: some carriers have enough energy to surmount the 3.1 eV Si/SiO\(_2\) barrier and become trapped in oxide.

The LDD (lightly doped drain) structure addresses this by spreading the lateral field peak. After gate patterning, a low-dose (\(10^{13}\;\text{cm}^{-2}\)) extension implant is made self-aligned to the gate edge, then nitride spacers are formed and the high-dose (\(10^{15}\;\text{cm}^{-2}\)) S/D implant is placed farther from the channel edge. The graded N\(^+\)/N\(^-\) drain profile extends the high-field region over a longer distance, reducing \(|\mathcal{E}_{max}|\) by 20–40% for the same \(V_{DS}\).

6.5 Subthreshold Conduction — Detailed Derivation

Below \(V_T\), the channel is not pinched off — it is weakly inverted. The inversion charge is:

\[ Q_n \approx -C_{ox}(V_{GS}-V_T)\exp\!\left(\frac{\psi_s - 2\phi_F}{V_T}\right) \quad [\psi_s \text{ slightly below } 2\phi_F] \]

More carefully, using the exact relationship between surface potential and gate voltage (through Poisson’s equation in depletion), the current in subthreshold flows primarily by diffusion (the drift component is negligible) and evaluates to:

\[ I_D = I_0 \frac{W}{L} e^{(V_{GS}-V_T)/(nV_T)}\left(1 - e^{-V_{DS}/V_T}\right) \]

where \(n = 1 + C_{dep}/C_{ox}\) and \(I_0 = \mu_n C_{ox}(n-1)V_T^2\). The subthreshold swing \(S\) is:

\[ S = nV_T\ln 10 = \left(1 + \frac{C_{dep}}{C_{ox}}\right) \times 60\;\text{mV/dec at 300 K} \]

The minimum is 60 mV/dec for \(C_{dep} \to 0\) (i.e., infinitely thin body or ideal gate control). Interface traps add an additional term: \(S = (1 + (C_{dep}+qD_{it})/C_{ox})\times 60\;\text{mV/dec}\).

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Chapter 7: MOSFET Frequency Response

7.1 Unity-Current-Gain Frequency \(f_T\)

The transit frequency is found by driving the gate with a small-signal current \(i_g = j\omega (C_{gs}+C_{gd})v_{gs}\) and measuring the short-circuit drain current \(i_d = g_m v_{gs}\):

\[ |h_{21}| = \frac{|i_d|}{|i_g|} = \frac{g_m}{\omega(C_{gs}+C_{gd})} \]

Setting this to unity: \(f_T = g_m/[2\pi(C_{gs}+C_{gd})]\). Substituting the long-channel expressions:

\[ f_T = \frac{3\mu_n(V_{GS}-V_T)}{4\pi L^2} \propto \frac{1}{L^2} \]

For a short-channel device in velocity saturation where \(g_m = WC_{ox}v_{sat}\) and \(C_{gs} \approx WLC_{ox}\):

\[ f_T = \frac{v_{sat}}{2\pi L} \]

This is the fundamental upper limit for a given technology node. At 10 nm node: \(f_T = (10^7\;\text{cm/s})/(2\pi \times 10^{-6}\;\text{cm}) \approx 1.6\;\text{THz}\). Parasitic capacitances reduce the practical \(f_T\) by 2–5×.

7.2 Maximum Oscillation Frequency \(f_{max}\)

The power gain falls to unity at \(f_{max}\). The Mason unilateral gain is:

\[ U = \frac{|y_{21} - y_{12}|^2}{4[\text{Re}(y_{11})\text{Re}(y_{22}) - \text{Re}(y_{12})\text{Re}(y_{21})]} \]

For the simplified case \(y_{12} \approx j\omega C_{gd}\), \(y_{21} \approx g_m - j\omega C_{gd}\), \(y_{11} \approx j\omega(C_{gs}+C_{gd}) + 1/R_g\), \(y_{22} \approx g_{ds}\):

\[ f_{max} \approx \frac{f_T}{2}\sqrt{\frac{1}{g_{ds}R_g + g_m R_g C_{gd}/(C_{gs}+C_{gd})}} \]

For a multi-finger layout with \(N_f\) fingers of width \(W_{finger} = W/N_f\):

\[ R_g = \frac{R_{sq}}{3N_f} \cdot \frac{W/N_f}{L} \]

Increasing \(N_f\) reduces \(R_g\) as \(1/N_f^2\) (both the resistance per finger and the number of parallel paths improve), dramatically increasing \(f_{max}\). This is the fundamental reason all RF power amplifier transistors use narrow multi-finger gate structures.

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Chapter 8: Bipolar Junction Transistor — Advanced Analysis

8.1 Gummel Plot and Saturation Current

The Gummel plot — \(I_C\) and \(I_B\) vs. \(V_{BE}\) on a logarithmic scale — is the most informative characterisation of BJT performance. In the ideal regime both currents are exponential in \(V_{BE}\) with the same thermal voltage:

\[ I_C = I_{s,C} e^{V_{BE}/V_T}, \qquad I_B = I_{s,B} e^{V_{BE}/V_T}, \qquad \beta_F = \frac{I_{s,C}}{I_{s,B}} \]

The collector saturation current:

\[ I_{s,C} = \frac{qAD_n n_i^2}{N_A W_B} \quad \text{(thin-base, uniform doping)} \]

The Gummel number generalises this to non-uniform base doping:

\[ G_B = \int_0^{W_B} \frac{N_A(x)}{D_n(x)}\,dx, \qquad I_{s,C} = \frac{qAn_i^2}{G_B} \]

A smaller Gummel number means higher collector current at the same \(V_{BE}\). In a graded-base HBT, the effective \(n_i^2\) (which depends on bandgap) varies with position, and the Gummel number integral must use the local \(n_i^2(x)\).

Deviations in the Gummel plot from the ideal slope \(1/V_T\) (at low \(V_{BE}\), ideality factor \(n>1\) in \(I_B\)) indicate space-charge recombination; at high \(V_{BE}\), the onset of high-level injection and series resistance is visible.

8.2 Current Gain Factors and their Trade-offs

The common-base current gain \(\alpha\) decomposes as:

\[ \alpha = \gamma \cdot \alpha_T \]

Emitter injection efficiency:

\[ \gamma = \frac{J_n^E}{J_n^E + J_p^E} = \frac{1}{1 + \frac{D_p^E N_B W_B}{D_n^B N_E W_E}} \cdot \frac{1}{1 + \frac{\tau_{nE}}{\tau_{pE}}\frac{D_{p}}{D_n}\frac{N_B}{N_E}\frac{W_B}{W_E}} \]

For practical purposes, maximising \(\gamma\) requires \(N_E \gg N_B\). However, heavy emitter doping triggers Auger recombination and bandgap narrowing, effectively reducing \(n_i^{2,eff}\) in the emitter and bringing \(J_p^E\) back up. The net effect is that \(\gamma\) saturates and then decreases for \(N_E > 10^{18}\;\text{cm}^{-3}\) — the emitter crowding and Auger-limited regime.

Base transport factor:

\[ \alpha_T = \frac{1}{\cosh(W_B/L_n)} \approx 1 - \frac{W_B^2}{2L_n^2} \quad (W_B \ll L_n) \]

Maximising \(\alpha_T\) requires \(W_B \ll L_n\). In Si BJTs, \(W_B\) is set lithographically (double-diffusion) or epitaxially, typically 50–200 nm in modern devices.

The common-emitter gain \(\beta = \alpha/(1-\alpha)\). The trade-off: increasing \(N_B\) (for lower \(r_b\) and better \(f_{max}\)) decreases \(\gamma\) and hence \(\beta\). HBTs escape this trade-off by using bandgap engineering.

8.3 Early Effect — Complete Analysis

The Early voltage appears because the effective base width \(W_B\) is a function of \(V_{CE}\):

\[ \frac{dW_B}{dV_{CE}} = -\frac{dx_{BC}}{dV_{CE}} = -\frac{1}{2}\sqrt{\frac{\varepsilon_s}{2qN_C(V_{bi,BC}+V_{CE})}} \]

The change in collector current:

\[ \frac{dI_C}{dV_{CE}} = -I_C \frac{1}{W_B}\frac{dW_B}{dV_{CE}} = I_C \cdot \frac{C_{BC}}{qN_B W_B} \]

where \(C_{BC}\) is the base-collector capacitance per unit area. The Early voltage:

\[ V_A = I_C \bigg/ \frac{dI_C}{dV_{CE}} = \frac{qN_A W_B}{C_{BC}/A} \]

Increasing \(N_A W_B\) (the base Gummel number) increases \(V_A\) but also decreases \(\beta\) — the fundamental \(\beta V_A\) product is a technology-dependent figure of merit. For silicon BJTs, \(\beta V_A \approx 5000\;\text{V}\); SiGe HBTs achieve \(\beta V_A > 10^5\;\text{V}\).

8.4 Kirk Effect — Base Push-Out

In the collector drift region (n-doped to \(N_C\)), the electron density under high injection is not small. Space charge in the drift region is:

\[ \rho = q(N_D - n + p) \approx q\left(N_C - \frac{J_C}{qv_{sat}}\right) \]

The sign of this space charge determines whether the electric field supports or opposes the collector depletion. When \(J_C > qN_C v_{sat}\), the space charge sign reverses: positive space charge now appears on the n-side of the BC junction, pushing the effective base boundary into the collector — the Kirk effect. The base widens until a new equilibrium is found with a heavily injected n-type region acting as part of the base. As \(W_B\) increases, \(f_T\) drops precipitously and \(\beta\) may collapse.

The Kirk current density threshold: \(J_{Kirk} \approx qN_C v_{sat}\). For \(N_C = 10^{16}\;\text{cm}^{-3}\): \(J_{Kirk} = 1.6\times10^{-19}\times10^{16}\times10^7 = 1.6\;\text{kA/cm}^2\). To push this limit higher, increase \(N_C\) or use a different collector geometry — but higher \(N_C\) reduces \(BV_{CEO}\) (collector-emitter breakdown with base open). This \(J_{Kirk}\)–\(BV_{CEO}\) trade-off is the power-speed trade-off of bipolar transistors.

8.5 Hybrid-\(\pi\) Model — Parameter Extraction

The complete hybrid-\(\pi\) model parameters are:

\[ g_m = \frac{I_C}{V_T}, \quad r_\pi = \frac{\beta}{g_m}, \quad r_o = \frac{V_A}{I_C} \]\[ C_\pi = C_{jE} + g_m \tau_F, \quad C_\mu = C_{jC} \]

where \(C_{jE}\) and \(C_{jC}\) are the emitter-base and base-collector junction capacitances. The forward transit time \(\tau_F = W_B^2/(2D_n)\) for a uniform base, or \(\tau_F = W_B^2/(2D_n\eta)\) for a graded base with built-in field factor \(\eta = \Delta E_g/(k_BT)\ln(\Delta E_g/k_BT - 1)\).

The unity-current-gain frequency (measured via S-parameters as the frequency where \(|h_{21}| = 1\)):

\[ f_T = \frac{1}{2\pi\tau_{EC}} = \frac{1}{2\pi\left[\tau_F + \frac{k_BT}{qI_C}(C_{jE}+C_{jC}) + C_{jC}(R_E+R_C)\right]} \]

Plotting \(1/(2\pi f_T)\) vs. \(1/I_C\) (at fixed \(V_{CE}\)) gives a straight line with y-intercept \(\tau_F + C_{jC}(R_E+R_C)\) and slope \(k_BT(C_{jE}+C_{jC})/q\).

8.6 BJT Saturation and Switching Transients

In saturation, both junctions are forward-biased. The base charge has two components:

\[ Q_{tot} = Q_F + Q_R = I_C\tau_F + I_{EC}\tau_R \]

where \(\tau_R\) is the reverse transit time (much larger than \(\tau_F\) — the transistor is slow in reverse). The degree of saturation is characterised by the overdrive factor \(OD = I_{B,forced}/I_{B,sat}\), where \(I_{B,sat} = I_{C,forced}/\beta_F\). Deep saturation (\(OD \gg 1\)) stores large \(Q_R\) and produces long saturation delay time \(t_s\).

The Schottky transistor uses a Schottky diode between base and collector to clamp \(V_{BC} \leq 0.4\;\text{V}\), preventing deep saturation. The diode diverts excess base current directly to the collector, keeping \(Q_R \approx 0\) and eliminating \(t_s\). This was the basis of Schottky TTL logic, which achieved nanosecond switching.

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Chapter 9: Heterojunctions and SiGe HBTs

9.1 Band Alignment — Anderson Model and Beyond

The Anderson model predicts band offsets purely from bulk electron affinities. For real heterojunctions, interface dipoles modify the band alignment. The common anion rule (empirical) states that heterojunctions sharing an anion (e.g., GaAs/AlAs both have As) tend to have most of the band offset in the conduction band. The more rigorous approach uses natural band alignments calculated from bulk energy levels referenced to vacuum.

For SiGe/Si with \(x\) fraction Ge in Si\(_{1-x}\)Ge\(_x\):

\[ \Delta E_g \approx 0.74x\;\text{eV}, \quad \Delta E_v \approx 0.74x\;\text{eV}, \quad \Delta E_c \approx 0 \]

The entire bandgap reduction appears in the valence band. This is fortuitous for NPN HBTs: the narrower-gap SiGe base lowers the valence band, creating a barrier that suppresses hole injection back into the emitter. For a 20% Ge base: \(\Delta E_g = 0.148\;\text{eV}\), giving a gain enhancement factor:

\[ \frac{\beta_{HBT}}{\beta_{BJT}} = \exp\!\left(\frac{\Delta E_g}{k_BT}\right) \approx e^{0.148/0.026} \approx 320 \]

This factor is so large that the HBT can use a base doped 300× more heavily than the emitter and still maintain higher \(\beta\) — reversing the design rule of the homojunction BJT.

9.2 Graded Ge Profile and Transit Time Reduction

If the Ge fraction increases linearly from 0 at the emitter end to \(x_{max}\) at the collector end of the base, the resulting bandgap gradient creates a built-in quasi-electric field:

\[ \mathcal{E}_{drift} = \frac{\Delta E_g}{qW_B} = \frac{0.74 x_{max}}{W_B}\;\text{eV/cm} \cdot \frac{1}{q} \]

This drift field accelerates electrons across the base. The transit time in a linearly graded base with drift field \(\mathcal{E}_{drift}\) is:

\[ \tau_F = \frac{W_B^2}{2D_n}\left[\frac{2k_BT}{\Delta E_g}\left(1 - \frac{k_BT}{\Delta E_g}\left(1 - e^{-\Delta E_g/k_BT}\right)\right)\right] \]

For \(\Delta E_g \gg k_BT\): \(\tau_F \approx W_B^2 k_BT/(D_n \Delta E_g)\), reduced from the uniform-base value by \(\Delta E_g/(2k_BT)\). At \(\Delta E_g = 0.15\;\text{eV}\): reduction factor \(\approx 0.15/(2\times0.026) \approx 3\times\). Combined with the ability to use a narrow base (because relaxed \(\beta\) requirement allows lower \(N_E\)), \(f_T\) can be 5–10× higher than a comparable homojunction device.

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Chapter 10: Microelectronic Fabrication

10.1 Crystal Growth — CZ and FZ

The Czochralski (CZ) process grows single-crystal silicon by slowly pulling a seed crystal from molten silicon polysilicon while rotating both seed and crucible. Diameter and doping are controlled by pull rate and dopant addition. The segregation coefficient \(k_0 = C_{solid}/C_{liquid}\) governs how dopants distribute: since \(k_0 < 1\) for most donors (P: 0.35, As: 0.3), the melt enriches as growth proceeds, causing higher doping near the tail of the ingot. The Scheil equation:

\[ C_s(f) = k_0 C_0 (1-f)^{k_0-1} \]

where \(f\) is the fraction solidified, describes this non-uniformity. For boron (\(k_0 = 0.8\)), the profile is much more uniform.

Float-zone (FZ) silicon avoids the silica crucible and achieves \(\sim 10\times\) lower oxygen (\(< 10^{16}\;\text{cm}^{-3}\)) and carbon content. The molten zone is passed along a polysilicon rod; resistivity can exceed \(10^4\;\Omega\cdot\text{cm}\). Used for power devices requiring very lightly doped substrates.

10.2 Thermal Oxidation — Deal–Grove Model

The Deal–Grove parabolic-linear growth model considers three transport steps in series: (1) oxidant transport through gas phase (fast), (2) diffusion through existing SiO\(_2\) at rate \(D/d_{ox}\), and (3) reaction at Si surface at rate \(k_s\). Setting up the flux balance in steady state:

\[ J = D\frac{C^* - C_s}{d_{ox}} = k_s C_s \]

leads to \(C_s = C^*/(1 + k_s d_{ox}/D)\). The growth rate \(dx_{ox}/dt = k_s C_s/N_1\):

\[ \frac{dx_{ox}}{dt} = \frac{B/A}{1 + x_{ox}/A/2} \]

This integrates to:

\[ x_{ox}^2 + A x_{ox} = B(t + \tau) \]

where \(A = 2D/k_s\) (linear rate constant divided by the parabolic), \(B = 2DC^*/N_1\) (parabolic rate constant), and \(\tau = (x_{i}^2 + Ax_i)/B\) accounts for any initial oxide of thickness \(x_i\). Important values for silicon (dry O\(_2\), 1000°C): \(A \approx 0.165\;\mu\text{m}\), \(B \approx 0.0117\;\mu\text{m}^2/\text{hr}\). For wet (H\(_2\)O, 1000°C): \(A \approx 0.226\;\mu\text{m}\), \(B \approx 0.287\;\mu\text{m}^2/\text{hr}\).

Oxidation consumes silicon. For every nm of SiO\(_2\) grown, 0.44 nm of Si is consumed, because the molar volume of SiO\(_2\) (27 cm\(^3\)/mol) exceeds that of Si (12 cm\(^3\)/mol) by a factor of 2.27. This is critical for STI depth budgets and gate dielectric interface positioning.

10.3 Photolithography — Resolution and Process

The Rayleigh resolution criterion \(R = k_1\lambda/NA\) and depth-of-focus \(DOF = k_2\lambda/NA^2\) define the process window. In 193 nm immersion (water between lens and wafer, \(n_{H_2O} = 1.44\), \(NA = n\sin\theta_{max} = 1.35\)):

\[ R \approx k_1 \frac{193\;\text{nm}}{1.35} \approx 40\;\text{nm} \quad (k_1 = 0.28) \]

Below this limit, multiple patterning is used:

• LELE (Litho-Etch-Litho-Etch): the pattern is split into two interleaved masks printed sequentially. Doubles effective resolution to \(\sim 20\;\text{nm}\) pitch.
• SADP (Self-Aligned Double Patterning): a conformal spacer is deposited on mandrel features; removing the mandrel leaves spacers at half the mandrel pitch. Achieves 1:1 pitch halving without a second mask alignment.
• EUV (13.5 nm): plasma-generated extreme ultraviolet from tin droplet laser-produced plasma. At \(NA = 0.33\), \(k_1 = 0.35\): \(R \approx 14\;\text{nm}\). High-NA EUV (\(NA = 0.55\)) targets sub-8 nm resolution.

10.4 Diffusion and Ion Implantation

Gaussian diffusion from a thin implanted source of dose \(Q\):

\[ C(x,t) = \frac{Q}{\sqrt{\pi Dt}}\exp\!\left(-\frac{x^2}{4Dt}\right) \]

The diffusivity \(D(T) = D_0\exp(-E_a/k_BT)\) is strongly temperature-dependent. For the junction depth in background doping \(N_B\):

\[ x_j = 2\sqrt{Dt}\sqrt{\ln(C_{max}/N_B)} = 2\sqrt{Dt}\sqrt{\ln\!\left(\frac{Q}{N_B\sqrt{\pi Dt}}\right)} \]

Transient enhanced diffusion (TED): post-implant damage creates interstitials that greatly accelerate boron diffusion during the initial portion of the anneal (“excess interstitials” from the plus-one model). TED increases \(x_j\) beyond the simple Gaussian prediction by 2–5× for low-energy boron. TED is suppressed by: (1) carbon co-implantation (traps interstitials), (2) millisecond flash or laser annealing (insufficient time for interstitial diffusion).

Ion implantation provides precise dose control (\(\pm 0.5\%\) routinely) and arbitrary depth positioning by selecting ion energy. The projected range and straggle are tabulated in SRIM/TRIM Monte Carlo calculations. Post-implant annealing is done in two steps: (1) a low-temperature pre-amorphisation or damage anneal, and (2) a spike RTA (ramp to 1050–1075°C, hold 1–5 s) for activation with minimal diffusion.

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Chapter 11: Optoelectronic Devices

11.1 Optical Absorption and Emission

The absorption coefficient of a direct-gap semiconductor near the band edge (parabolic band approximation):

\[ \alpha(h\nu) = C_0 \sqrt{h\nu - E_g}, \quad h\nu \geq E_g \]

where \(C_0 = q\sqrt{2m_r^{*3/2}}/(\pi\hbar^2\varepsilon_{opt}^{1/2}m_0)\) and \(\varepsilon_{opt}\) is the optical dielectric constant. For GaAs, \(\alpha \approx 10^4\;\text{cm}^{-1}\) at 10 meV above \(E_g\), growing to \(\sim 10^5\;\text{cm}^{-1}\) at 100 meV above \(E_g\). The absorption length \(1/\alpha\) ranges from 10 nm to 1 \(\mu\)m across this range.

For silicon (indirect gap), the absorption must be phonon-assisted:

\[ \alpha_{indirect}(h\nu) \propto (h\nu - E_g \pm \hbar\omega_{phonon})^2 \]

The quadratic onset and the requirement for phonon participation give \(\alpha \approx 10^2\;\text{cm}^{-1}\) at 1.12 eV, reaching \(\sim 10^3\;\text{cm}^{-1}\) only 100 meV above \(E_g\). This weak absorption makes Si photodetectors require thick absorption layers and is why direct-gap materials (Ge, InGaAs) dominate photonic applications despite the dominance of Si in electronics.

11.2 LED Physics and Efficiency

In an LED, the radiative recombination rate in the active region is \(R_{rad} = Bnp\). Under high injection (carrier densities much greater than background doping), \(n \approx p = \Delta n\) and \(R_{rad} = B(\Delta n)^2\). The internal quantum efficiency:

\[ \eta_{IQE} = \frac{R_{rad}}{R_{rad} + R_{SRH} + R_{Auger}} = \frac{B(\Delta n)^2}{B(\Delta n)^2 + A(\Delta n) + C(\Delta n)^3} \]

The ABC model for IQE uses: \(A\) (SRH coefficient, \(\text{s}^{-1}\)), \(B\) (radiative, \(\text{cm}^3/\text{s}\)), \(C\) (Auger, \(\text{cm}^6/\text{s}\)). At low carrier density, SRH dominates (\(\eta \propto \Delta n\)); at intermediate density, \(\eta_{IQE}\) peaks (\(\sim B/\sqrt{AC}\)); at high density, Auger dominates and \(\eta_{IQE}\) falls — the LED droop phenomenon critical in high-power InGaN LEDs.

Light extraction. Only light emitted within the escape cone (\(\theta < \theta_c = \arcsin(1/n_s)\)) can escape from a flat semiconductor surface. For GaAs (\(n_s = 3.5\)): \(\theta_c = 16.6°\), and the fraction of light in the escape cone:

\[ \eta_{ext} = \frac{1 - \cos\theta_c}{2} \approx \frac{1}{4n_s^2} = \frac{1}{4\times12.25} \approx 2\% \]

Light that is not extracted undergoes total internal reflection and is eventually absorbed by the substrate. Solutions include: chip shaping (hemispherical or truncated cone geometry to increase the escape cone angle for more ray directions), surface texturing (disrupts the planar interface so rays have multiple chances to escape), and photonic crystal structures (engineer the photon density of states to favour upward emission).

11.3 PIN Photodiode — Complete Analysis

The photocurrent generated in a PIN diode has three components:

1. Carriers generated in the depletion (I) region: immediately swept out by the field. Contribution to photocurrent: \(I_{dep} = qG_{opt}W_I A\) where \(G_{opt} = \Phi_0\alpha e^{-\alpha x}\) integrated over the I region.

2. Minority carriers generated within one diffusion length of the p and n regions: diffuse to the junction and are swept across. This contribution is slower (diffusion-limited) and limits bandwidth at low reverse bias.

3. Carriers generated deeper than \(L_p + W_I + L_n\): are too far from the junction and recombine before contributing.

The total quantum efficiency (for \(\alpha W_I \ll 1\) and thin p and n layers with reflectivity \(R\)):

\[ \eta_q \approx (1-R)(1 - e^{-\alpha W_I}) \]

For high efficiency, \(\alpha W_I \gg 1\), but this requires a thick I region which limits bandwidth. Conversely, for wide bandwidth, a thin I region minimises transit time \(\tau_{tr} = W_I/v_{sat}\) and junction capacitance \(C_j = \varepsilon_s A/W_I\), but at the cost of low quantum efficiency. An optimised tradeoff is achieved when \(f_{transit} = f_{RC}\).

11.4 Solar Cell Efficiency — Shockley–Queisser Analysis

The Shockley–Queisser limit is derived by considering a solar cell as a blackbody photon absorber/emitter in contact with the sun (6000 K) and the Earth (300 K). The absorbed photocurrent (all photons with \(h\nu > E_g\) absorbed, one electron-hole pair per photon):

\[ J_{sc} = q\int_{E_g}^\infty N_{ph}(E)\,dE \]

where \(N_{ph}(E)\) is the solar photon flux at AM1.5G spectrum. The maximum \(V_{oc}\) is limited by detailed balance: the cell must radiate as a blackbody at 300 K at the elevated electron/hole quasi-Fermi level splitting \(qV_{oc}\).

The resulting efficiency limit is:

\[ \eta_{SQ} = \frac{J_{mp}V_{mp}}{P_{sun}} \leq 33\% \quad \text{at } E_g \approx 1.34\;\text{eV} \]

The three main losses are: (1) photons with \(h\nu < E_g\) — not absorbed; (2) photons with \(h\nu > E_g\) — thermalization loss of \((h\nu - E_g)\) per photon; (3) voltage loss — the electrochemical potential difference \(qV_{oc} < E_g\) due to radiative recombination.

Multi-junction strategies divide the solar spectrum among junctions with different \(E_g\), minimising thermalization loss. A three-junction InGaP (1.85 eV)/GaAs (1.42 eV)/Ge (0.67 eV) cell has a theoretical limit exceeding 50% under concentrated illumination. Research cells have exceeded 47% efficiency under 143-sun concentration.

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Chapter 12: Power Devices

12.1 Power MOSFET — DMOS Structure

The lateral MOSFET topology fails for power applications because lateral integration of a high-voltage drift region requires impractically large chip area. The double-diffused MOS (DMOS) uses vertical current flow:

1. N\(^+\) source at top surface
2. P-body (channel region) formed by double diffusion (P-body diffuses further than N\(^+\) source, creating a self-aligned P channel under N\(^+\))
3. N-drift region (lightly doped, supports off-state voltage)
4. N\(^+\) substrate (drain contact at wafer bottom)

In the on-state, channel forms at P-body surface under the gate, current flows vertically through N\(^-\) drift to drain. The on-resistance is dominated by the drift region:

\[ R_{drift} \approx \frac{\rho_{drift} L_{drift}}{A} = \frac{L_{drift}}{q\mu_n N_D A} \]

The silicon limit for a 1D drift region: the depletion approximation gives \(BV = \varepsilon_s \mathcal{E}_{crit}^2/(2qN_D)\), so \(N_D = \varepsilon_s \mathcal{E}_{crit}^2/(2qBV)\), and \(\rho_{drift} = 1/(q\mu_n N_D)\). The specific on-resistance:

\[ R_{on,sp} = \frac{4BV^2}{\mu_n\varepsilon_s\mathcal{E}_{crit}^3} \]

For silicon (\(\mathcal{E}_{crit} = 3\times10^5\;\text{V/cm}\)): \(R_{on,sp} \approx 2\times10^{-8}BV^{2.5}\;\Omega\text{cm}^2\). At 600 V: \(R_{on,sp} \approx 20\;\text{m}\Omega\text{cm}^2\). Wide-bandgap GaN (\(\mathcal{E}_{crit} = 3\times10^6\;\text{V/cm}\)) reduces this by \((3\times10^6/3\times10^5)^3 = 1000\times\) at the same voltage.

12.2 IGBT Operation and Switching

The IGBT is modelled as a PNP transistor (p\(^+\) substrate / n-drift / p-body) driven by a MOSFET. The MOSFET provides the base current to the PNP; the PNP’s collector current is the hole current flowing from the p\(^+\) substrate through the n-drift region. This hole injection causes conductivity modulation — the drift region’s effective resistivity drops from its physical value to \(\rho_{eff} \approx q\mu_n \Delta n\) where \(\Delta n \gg N_D\). This allows IGBTs to achieve \(V_{CE,sat} \approx 1.5–2\;\text{V}\) for 1200 V devices, compared to \(R_{on,sp}\times J > 10\;\text{V}\) for a MOSFET at the same rating.

The turn-off waveform has a characteristic current tail: as \(V_{GE}\) falls below threshold, the MOSFET turns off. But the minority holes injected into the drift region continue to flow as the PNP transistor recombines them. The tail current decays with time constant \(\tau_{HL}\) (high-level lifetime). Carrier lifetime engineering (electron irradiation, proton bombardment, or Pt diffusion) reduces \(\tau_{HL}\) to achieve faster switching, but increases \(V_{CE,sat}\) — the fundamental switching speed vs. conduction loss trade-off of IGBTs.

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Chapter 13: CMOS Technology Integration

13.1 Well Structures and Isolation

Modern CMOS uses shallow trench isolation (STI) rather than LOCOS (local oxidation of silicon). STI trenches (\(\sim 300\;\text{nm}\) deep, \(\sim 100\;\text{nm}\) wide) are filled with CVD oxide and planarised by chemical-mechanical polishing (CMP). STI eliminates the bird’s beak encroachment of LOCOS and allows much tighter packing.

Twin-well implants: retrograde N-well (phosphorus at 500–700 keV to place peak ~0.5–1 \(\mu\)m deep) and P-well (boron). A deep N-well ring surrounds the P-well of NMOS transistors to provide full isolation from substrate noise — critical in RF and mixed-signal circuits.

13.2 Advanced Gate Stacks

The transition from SiO\(_2\) to high-\(\kappa\)/metal gate was driven by direct tunneling becoming too large below EOT \(\approx 1.2\;\text{nm}\). Intel’s 45 nm process (2007) introduced HfO\(_2\)/metal gate: physical \(t_{HK} \approx 3\;\text{nm}\) with \(\kappa \approx 20\) gives EOT = \((3.9/20)\times3 = 0.58\;\text{nm}\), reducing tunneling leakage by >1000× compared to a SiO\(_2\) film of the same EOT.

Metal gate (TiN, TaN, W, or their alloys) replaces polysilicon to: (1) eliminate poly-depletion (poly at the gate dielectric interface depletes under bias, adding \(\sim 0.3–0.5\;\text{nm}\) of equivalent oxide thickness), (2) allow independent tuning of NMOS and PMOS work functions. Gate-first vs. gate-last (replacement metal gate) process flows: gate-last allows high-temperature S/D anneals before the thermally sensitive metal is deposited.

13.3 FinFET Design Considerations

The FinFET gate wraps around a fin of height \(H_{fin}\) and width \(W_{fin}\). The natural length scale for electrostatic control:

\[ \lambda_{fin} \approx \sqrt{\frac{\varepsilon_{Si} W_{fin} t_{ox}}{2\varepsilon_{ox}}} \quad \text{(double-gate approximation)} \]

SCEs are suppressed when \(L > 5\lambda_{fin}\). With \(W_{fin} = 7\;\text{nm}\) and \(t_{ox} = 1.5\;\text{nm}\) EOT:

\[ \lambda_{fin} \approx \sqrt{\frac{11.7\times7\times1.5}{2\times3.9}} = \sqrt{15.8} \approx 3.97\;\text{nm} \]

This allows channel lengths as short as 20 nm with adequate electrostatic control. The FinFET is a naturally undoped channel device (no channel doping needed for threshold control, since the gate-all-around geometry provides sufficient electrostatic control). This eliminates random dopant fluctuation (RDF) — a major source of VT variability in planar MOSFETs — significantly improving device-to-device matching.

Threshold voltage is tuned entirely through gate work function (metal alloy composition) and fin geometry, enabling different \(V_T\) flavors within the same technology.

The FinFET’s discrete quantisation of width (each fin contributes a fixed \(W_{eff} = 2H_{fin}+W_{fin}\)) changes device sizing from a continuous to a discrete design variable. In place of the traditional \(W/L\) ratio, designers choose the number of fins \(N_{fin}\) and the gate length \(L\), with \(N_{fin} \in \mathbb{Z}^+\). This discretization complicates analog design (where precise W/L ratios are needed for matching) but is manageable in digital logic.

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Chapter 14: Interconnects and Parasitics

14.1 Interconnect Scaling and RC Delay

As transistors have shrunk, interconnect wires have not scaled proportionally in thickness (to keep resistance manageable). The result is that interconnect RC delay now dominates total chip delay at advanced nodes. For a metal wire of resistivity \(\rho_m\), cross-sectional area \(A_w = w\times h\), and capacitance per unit length \(C_{line}\):

\[ \tau_{RC} = R \cdot C = \frac{\rho_m}{A_w} \cdot C_{line} \cdot L_{wire}^2 \]

The square dependence on \(L_{wire}\) is why long global wires are dramatically slower than short local wires. Repeater insertion (buffer amplifiers at intervals \(\lambda_{opt} = \sqrt{2\rho_m C_{line} L_{wire}/\tau_{inv}}\)) reduces the effective delay to linear in \(L_{wire}\).

Copper (resistivity \(\rho_{Cu} = 1.72\;\mu\Omega\text{cm}\)) replaced aluminum (2.7 \(\mu\Omega\text{cm}\)) starting at the 180 nm node. At linewidths below 30 nm, the effective Cu resistivity increases dramatically due to electron scattering at grain boundaries and sidewalls (the Fuchs–Sondheimer and Mayadas–Shatzkes models). Alternative materials (Ru, Mo, W) with lower bulk resistivity sensitivity to grain-boundary scattering are under investigation for sub-5 nm node wires.

14.2 Electromigration

Electromigration is the mass transport of metal atoms driven by momentum transfer from conducting electrons (electron wind force). The mean time to failure under current density \(J\) and temperature \(T\) follows Black’s equation:

\[ MTF = A \cdot J^{-n} \exp\!\left(\frac{E_a}{k_BT}\right) \]

where \(n \approx 2\) for Al and \(\sim 1\) for Cu, and \(E_a \approx 0.7\;\text{eV}\) for Cu grain boundary diffusion. The design limit in modern Cu interconnects is \(J_{max} \approx 5\times10^6\;\text{A/cm}^2\) at 105°C for a 10-year operating lifetime. Exceeding this limit causes void formation (open circuit) at the cathode end or hillock formation at the anode.

Cu is encapsulated in a Ta/TaN barrier liner (deposited by PVD) to prevent Cu diffusion into the dielectric and silicon (Cu is a deep trap in Si — catastrophic for junction leakage). The barrier liner also provides adhesion.

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Chapter 15: Noise in Semiconductor Devices

15.1 Thermal Noise

Any resistor at temperature \(T\) generates Johnson–Nyquist (thermal) noise due to thermal fluctuations of charge carriers. The open-circuit noise voltage spectral density is:

\[ S_V(f) = 4k_BTR \quad [\text{V}^2/\text{Hz}] \]

This is white noise (flat spectrum) up to frequencies \(\sim k_BT/h \approx 6\;\text{THz}\) at room temperature, far above any practical device operating frequency. The short-circuit noise current spectral density is \(S_I = 4k_BT/R = 4k_BTG\).

For a MOSFET biased in saturation, the channel thermal noise is:

\[ S_{Id} = 4k_BT\gamma g_{d0} \]

where \(g_{d0} = \mu_n C_{ox}(W/L)(V_{GS}-V_T)\) is the zero-drain-bias channel conductance and \(\gamma \approx 2/3\) for long-channel devices. At short channel lengths, \(\gamma\) can increase substantially (velocity saturation, hot carriers), increasing the device noise. The input-referred noise voltage is \(S_{Vn} = S_{Id}/g_m^2 = 4k_BT\gamma/g_m\), motivating high \(g_m\) (large \(W/L\) and high \(I_D\)) for low-noise amplifier design.

15.2 Shot Noise

In a pn junction diode, the random arrival of carriers across the barrier gives shot noise:

\[ S_I = 2qI_{DC} \]

This is the Schottky formula. For a diode with total dc current \(I_{DC} = I_F - I_R\) (forward minus reverse component), shot noise represents the randomness of individual carrier crossings — a Poisson process. Shot noise appears in BJT base and collector currents, MOSFET gate current (due to oxide tunneling), and photodetector photocurrent.

15.3 Flicker (1/f) Noise

At low frequencies, most electronic devices exhibit flicker noise (also called \(1/f\) noise or pink noise) with a power spectral density:

\[ S_I(f) = \frac{K_F I_{DC}^\alpha}{f^\beta} \]

where \(K_F\) is a device-dependent constant, \(\alpha \approx 1–2\), \(\beta \approx 1\). In MOSFETs, the dominant mechanism is carrier number fluctuation due to trapping and de-trapping of electrons in oxide interface traps. The input-referred \(1/f\) voltage noise for a MOSFET:

\[ S_{Vn}^{1/f} = \frac{K_F}{W L C_{ox}^2 f} \]

The \(1/(WL)\) dependence means that large-area devices have lower \(1/f\) noise — important for analog amplifiers where the input transistor is often scaled to large area to minimise noise at the cost of speed.

The corner frequency \(f_c\) separates the \(1/f\) and thermal noise regimes: \(f_c = K_F g_m^2/(4k_BT\gamma g_{d0}WLC_{ox}^2)\). For MOSFETs, \(f_c\) is typically 1 MHz–1 GHz depending on technology and bias; for BJTs, it is much lower (1–100 kHz), making BJTs preferable in low-frequency precision circuits.

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Chapter 16: Advanced Topics — Quantum Confinement and 2DEG

16.1 Quantum Confinement in Inversion Layers

When a MOSFET is strongly inverted, the potential well at the Si/SiO\(_2\) interface confines electrons quantum-mechanically. The inversion layer thickness is comparable to the de Broglie wavelength of electrons (\(\sim 2–5\;\text{nm}\)), and the energy levels are quantised:

The Schrödinger equation in the triangular potential approximation (field \(\mathcal{E}_s\) at the surface):

\[ -\frac{\hbar^2}{2m_z^*}\frac{d^2\psi}{dz^2} + q\mathcal{E}_s z \cdot \psi = E\psi, \quad z > 0; \quad \psi(0) = 0 \]

gives quantised subband energies approximately:

\[ E_j \approx \left(\frac{\hbar^2}{2m_z^*}\right)^{1/3} \left(\frac{3\pi q\mathcal{E}_s}{2}\right)^{2/3}\left(j + \frac{3}{4}\right)^{2/3} \]

For silicon with \(m_z^* = 0.916 m_0\) (longitudinal mass, for the two-fold degenerate valleys oriented perpendicular to (100) surface) and \(\mathcal{E}_s = 5\times10^5\;\text{V/cm}\): \(E_0 \approx 60\;\text{meV}\). This means the ground subband is 60 meV above the classical band edge, effectively increasing the threshold voltage by this amount (the quantum correction to \(V_T\)).

Furthermore, the maximum of the electron probability density is not at the interface (\(z=0\)) but at \(z \approx 1–2\;\text{nm}\), reducing interface scattering. This is one reason extremely thin gate dielectrics can still achieve high mobility — the electrons are not residing exactly at the defect-laden interface.

16.2 Two-Dimensional Electron Gas (2DEG) in HEMT

In a high electron mobility transistor (HEMT), a thin wide-gap semiconductor (AlGaAs, AlGaN) is grown epitaxially on a narrow-gap semiconductor (GaAs, GaN). Ionised donors in the AlGaAs supply electrons that fall into the potential well at the AlGaAs/GaAs interface, forming a two-dimensional electron gas (2DEG).

The 2DEG electrons are spatially separated from the ionised donors (which remain in the AlGaAs). Because the electrons are not co-located with charged impurities, impurity scattering is negligible, and the electron mobility is extremely high. At 300 K, GaAs 2DEG mobilities exceed \(8000\;\text{cm}^2/\text{Vs}\) (vs. \(\sim 4000\;\text{cm}^2/\text{Vs}\) for bulk n-GaAs); at 4 K, 2DEG mobilities above \(10^7\;\text{cm}^2/\text{Vs}\) have been measured, enabling the observation of the quantum Hall effect.

The 2DEG sheet charge density is controlled by the gate voltage (depletion gate):

\[ n_s = \frac{C_{gate}}{q}(V_{gs} - V_{off}) \]

where \(V_{off}\) is the threshold (pinch-off) voltage and \(C_{gate} = \varepsilon_{AlGaAs}/(d_{AlGaAs} + \Delta d)\) with \(\Delta d\) accounting for the finite 2DEG wavefunction extent. HEMTs dominate microwave and millimeter-wave power amplification (cellular base stations, satellite communication, 5G/6G millimeter-wave) due to their high \(f_T\) and \(f_{max}\) (>1 THz for InAlAs/InGaAs systems).

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Chapter 17: Device Characterization Methods

17.1 Current–Voltage Measurement

The most basic device characterization is the dc \(I\)–\(V\) curve. For a MOSFET, a semiconductor parameter analyser (e.g., Keysight B1500A) sweeps \(V_{GS}\) and \(V_{DS}\) to generate the complete output and transfer characteristics. From these curves one extracts:

• Threshold voltage \(V_T\): from the linear extrapolation of the \(\sqrt{I_D}\)–\(V_{GS}\) curve in saturation, or the constant-current method (\(V_{GS}\) at \(I_D = 100\;\text{nA}\times W/L\)).
• Transconductance \(g_m\): \(\partial I_D/\partial V_{GS}\) at fixed \(V_{DS}\). Peak \(g_m\) and its location relative to \(V_T\) indicate SCE severity.
• Subthreshold swing \(S\): slope of \(\log I_D\) vs. \(V_{GS}\) below threshold.
• DIBL: shift in \(V_T\) (by constant-current method) between \(V_{DS} = 50\;\text{mV}\) and \(V_{DS} = 1\;\text{V}\), divided by 0.95 V.
• Channel length modulation \(\lambda\): slope of \(I_D\)–\(V_{DS}\) in saturation, normalised to \(I_D\).

17.2 Capacitance–Voltage Measurement

C-V measurement on a MOS capacitor provides information on oxide quality and interface properties. The frequency dispersion of the measured capacitance between high frequency (HF, \(>10\;\text{kHz}\)) and quasi-static (QS, dc ramp) gives the interface state density \(D_{it}\):

\[ D_{it}(E) = \frac{C_{ox}}{q^2 A}\left[\frac{1}{C_{HF}/C_{ox} - 1} - \frac{1}{C_{QS}/C_{ox} - 1}\right] \]

From the flatband voltage shift (relative to an ideal MOS capacitor with known \(\phi_{ms}\)):

\[ Q_{eff}/C_{ox} = V_{FB,ideal} - V_{FB,measured} \]

The slope of \(1/C^2\) vs. \(V_R\) in the Mott-Schottky plot determines the doping profile: \(N_D(W) = -2/(q\varepsilon_s A^2 \cdot d(1/C^2)/dV)\). Non-linear Mott-Schottky plots indicate non-uniform doping.

17.3 Hall Measurement

The Hall effect measures carrier type, concentration, and mobility simultaneously. A bar-shaped semiconductor sample carries current \(I_x\) in the \(x\)-direction while a magnetic field \(B_z\) is applied in the \(z\)-direction. The Lorentz force deflects carriers, building up a transverse Hall electric field:

\[ \mathcal{E}_H = R_H J_x B_z, \qquad R_H = \frac{r_H}{nq} \]

where \(r_H\) is the Hall scattering factor (\(\approx 3\pi/8\) for acoustic phonon scattering). The sign of \(V_H\) determines carrier type. The measured Hall mobility:

\[ \mu_H = \frac{|\mathcal{E}_H|}{J_x B_z} = r_H \mu_{conductivity} \]

For a van der Pauw structure (cloverleaf or square with contacts at edges), the sheet resistance \(R_{sh}\) and Hall coefficient \(R_H^{sheet}\) can be extracted from the four-probe measurement geometry regardless of sample shape, provided contacts are on the perimeter.

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Chapter 18: Selected Device Physics Problems with Solutions

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Chapter 19: Physical Limits and Future Directions

19.1 Fundamental Limits of MOSFET Scaling

Several physical limits constrain how far conventional MOSFET scaling can proceed:

Quantum tunneling through gate dielectric. The direct tunneling current density through a 1 nm SiO\(_2\) film exceeds \(10\;\text{A/cm}^2\), making the gate leakage comparable to or larger than the channel current. High-\(\kappa\) dielectrics address this but introduce new challenges (phonon scattering, remote Coulomb scattering, reliability).

Source-to-drain tunneling. At gate lengths below \(\sim 3–5\;\text{nm}\), electrons tunnel directly from source to drain through the channel barrier even when the gate is nominally off. This creates a hard lower bound on \(I_{off}\) that is independent of \(V_T\). First-principles simulations suggest this limit is reached around \(L_g \approx 3\;\text{nm}\) for silicon.

Thermal conductivity. Power density in modern processors exceeds \(100\;\text{W/cm}^2\), and local hot spots can reach much higher. The thermal resistance of the device stack limits how much power can be removed before junction temperature exceeds reliability limits (\(\sim 125°C\) for silicon). GaN and SiC, with thermal conductivities 3× higher than Si, enable higher power densities in power electronics.

Random dopant fluctuation. For a device with \(W = L = 10\;\text{nm}\) and \(x_d = 10\;\text{nm}\) at \(N_A = 10^{18}\;\text{cm}^{-3}\), the average number of dopant atoms in the channel is only \(N = N_A \times W\times L\times x_d = 10^{18}\times(10^{-6})^2\times10^{-6} = 10\). The Poisson fluctuation is \(\sqrt{N} = 3.16\), giving a \(V_T\) variation of \(\sigma_{VT} \approx (q/C_{ox})\sigma_N/\text{Area}\) — tens of mV for a planar bulk device. FinFETs and gate-all-around FETs use undoped channels, eliminating this variability.

19.2 Beyond-CMOS Devices

Tunnel FETs (TFETs): Use band-to-band tunneling as the injection mechanism instead of thermionic emission. The injection current is an exponential function of the gate-controlled tunneling probability rather than Boltzmann statistics, enabling sub-60 mV/dec subthreshold swing. Demonstrated in InAs/GaSb and Si systems; limited by low on-current and fabrication complexity.

Negative capacitance FETs (NC-FETs): A ferroelectric material (HfZrO\(_x\), BaTiO\(_3\)) in the gate stack can exhibit negative capacitance in certain bias conditions, effectively amplifying the gate voltage relative to the channel — an internal voltage step-up. This can reduce the subthreshold swing below 60 mV/dec. Commercialization prospects remain under investigation as ferroelectric reliability and hysteresis issues are addressed.

2D material FETs: Monolayer transition metal dichalcogenides (MoS\(_2\), WSe\(_2\)) are atomically thin semiconductors. Their ultimate thinness (\(\sim 0.7\;\text{nm}\)) eliminates source-to-drain tunneling concerns even at 1 nm gate lengths, and their dangling-bond-free surfaces enable ideal gate dielectric interfaces. IBM demonstrated a 1 nm gate-length MoS\(_2\) FET in 2016, though drive current remains much lower than Si FinFETs.

Gate-all-around (GAA) nanowire and nanosheet FETs: The natural evolution of FinFET, wrapping the gate fully around a nanowire or nanosheet provides maximum electrostatic control. Samsung’s 3 nm node (2022) uses stacked nanosheet GAA-FETs. The effective width per unit footprint is higher than FinFETs (multiple nanosheets stacked vertically), enabling higher drive current per chip area.

19.3 III-V Integration with Silicon

The high electron mobility in III-V compound semiconductors (InGaAs: \(\mu_n \approx 10000\;\text{cm}^2/\text{Vs}\) vs. Si: \(\sim 1400\;\text{cm}^2/\text{Vs}\)) makes them attractive for n-type channels in low-power CMOS. The challenge is co-integration with standard silicon: III-V materials have different crystal structure (zinc-blende vs. diamond cubic for Si), lattice mismatch, and incompatible processing.

Approaches include: (1) direct wafer bonding, (2) aspect-ratio trapping (growing III-V in narrow trenches to confine dislocations to the STI sidewalls), and (3) virtual substrates (graded SiGe buffers to accommodate lattice mismatch). PMOS using Ge channels (highest hole mobility, \(\mu_p \approx 1900\;\text{cm}^2/\text{Vs}\) vs. Si \(\sim 450\;\text{cm}^2/\text{Vs}\)) and NMOS using InGaAs represent a possible CMOS option beyond the 3 nm node if defect densities can be controlled to below \(\sim 10^6\;\text{cm}^{-2}\).

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Chapter 20: Worked Derivations and Supplementary Analysis

20.1 Full Derivation of the Shockley–Queisser Limit

The Shockley–Queisser (SQ) analysis begins from the principle of detailed balance. Under illumination, the solar cell must simultaneously absorb sunlight and emit radiation (as a thermodynamic consequence of being a blackbody emitter at temperature \(T_c = 300\;\text{K}\)).

The absorbed photocurrent density is the integral of the solar photon flux over all photon energies above the bandgap. Using the AM1.5G standard spectrum \(\Phi_{sun}(E)\) (photons per unit area per unit energy per unit time):

\[ J_{ph} = q\int_{E_g}^\infty \Phi_{sun}(E)\,dE \]

At short circuit and under the assumption of 100% internal quantum efficiency (every absorbed photon creates a collected electron-hole pair), \(J_{sc} = J_{ph}\).

The dark current is determined by the radiative recombination requirement. A solar cell at quasi-Fermi level splitting \(qV\) emits photons according to the generalized Planck law at temperature \(T_c\):

\[ \Phi_{emit}(E, V) = \frac{2E^2}{h^3 c^2} \frac{1}{\exp[(E - qV)/k_BT_c] - 1} \]

The emitted photocurrent from the cell (which constitutes the dark current):

\[ J_{dark}(V) = q\int_{E_g}^\infty \Phi_{emit}(E,V)\,dE \]

At \(V = 0\) (equilibrium emission): \(J_{dark}(0) = J_0\) (the radiative saturation current). For \(qV \gg k_BT_c\), the Bose–Einstein factor becomes Boltzmann and \(J_{dark}(V) \approx J_0 e^{qV/k_BT_c}\), recovering the diode equation. The total current:

\[ J(V) = J_{sc} - J_0\left(e^{qV/k_BT_c} - 1\right) \]

The open-circuit voltage is found by setting \(J = 0\):

\[ qV_{oc} = k_BT_c\ln\!\left(\frac{J_{sc}}{J_0} + 1\right) \approx k_BT_c\ln\!\left(\frac{J_{sc}}{J_0}\right) \]

Since \(J_0\) is determined by the cell’s emission at 300 K (proportional to \(e^{-E_g/k_BT_c}\)) and \(J_{sc}\) is determined by absorption of the much hotter solar spectrum (\(T_s \approx 6000\;\text{K}\)), the ratio \(J_{sc}/J_0\) is very large for materials with \(E_g\) near the optimum. The resulting \(V_{oc}\) is typically 75–85% of \(E_g/q\).

The efficiency:

\[ \eta = \frac{J_{mp}V_{mp}}{P_{in}} = \frac{FF \cdot J_{sc} \cdot V_{oc}}{P_{in}} \]

Numerically maximising \(\eta\) over \(E_g\) with \(P_{in} = 100\;\text{mW/cm}^2\) (AM1.5G) gives the famous SQ curve with a peak at \(E_g \approx 1.34\;\text{eV}\) (\(\eta_{max} \approx 33.7\%\)). For silicon (\(E_g = 1.12\;\text{eV}\)), the SQ limit is about 29.4%; for GaAs (\(E_g = 1.42\;\text{eV}\)), it is about 33.5%.

20.2 Derivation of the BJT Unity-Current-Gain Frequency

Starting from the full hybrid-\(\pi\) model of the NPN BJT, drive the base with small-signal current \(i_b\) and short-circuit the collector (load \(Z_L = 0\)). The base-emitter voltage developed is:

\[ v_{be} = i_b \cdot \left(r_\pi \| \frac{1}{j\omega(C_\pi + C_\mu)}\right) \]

The collector current for a short-circuit load (where \(v_{ce} = 0\) removes the \(C_\mu\) Miller effect from the drain):

\[ i_c = g_m v_{be} - j\omega C_\mu v_{be} \approx g_m v_{be} \quad (\omega \ll g_m/C_\mu) \]

The base current is:

\[ i_b = v_{be}\left(\frac{1}{r_\pi} + j\omega(C_\pi + C_\mu)\right) \]

The short-circuit current gain magnitude:

\[ |h_{21}(\omega)| = \frac{|i_c|}{|i_b|} = \frac{g_m}{\sqrt{(1/r_\pi)^2 + \omega^2(C_\pi+C_\mu)^2}} \]

At the \(3\;\text{dB}\) frequency \(\omega_\beta = 1/(r_\pi(C_\pi+C_\mu))\), the current gain equals \(\beta/\sqrt{2}\). For \(\omega \gg \omega_\beta\):

\[ |h_{21}| \approx \frac{g_m}{\omega(C_\pi+C_\mu)} \]

Setting \(|h_{21}| = 1\) gives the transit frequency:

\[ \omega_T = \frac{g_m}{C_\pi + C_\mu} = \frac{1}{\tau_F + (C_{jE}+C_{jC})/g_m} \]

For a device at \(I_C = 1\;\text{mA}\) with \(g_m = 38.5\;\text{mA/V}\), \(\tau_F = 5\;\text{ps}\), \(C_{jE} = 20\;\text{fF}\), \(C_{jC} = 5\;\text{fF}\):

\[ f_T = \frac{1}{2\pi\left[5\times10^{-12} + \frac{25\times10^{-15}}{38.5\times10^{-3}}\right]} = \frac{1}{2\pi\times5.65\;\text{ps}} = 28.1\;\text{GHz} \]

The device is transit-time limited at this current density. Increasing \(I_C\) reduces the \(C/g_m\) term, and \(f_T\) rises until the Kirk effect begins to degrade \(\tau_F\) — the characteristic peak in the \(f_T\)–\(I_C\) curve.

20.3 Threshold Voltage Sensitivity to Process Variations

In manufacturing, the threshold voltage is subject to variability from multiple sources. Understanding and controlling \(\sigma_{VT}\) is critical for SRAM cell stability and analog matching. The main contributors to \(\sigma_{VT}\) in a planar bulk MOSFET are:

Random dopant fluctuation (RDF). The number of dopant atoms in the depletion volume beneath the channel is a random variable with Poisson statistics. For \(N_{avg}\) atoms on average, the standard deviation is \(\sigma_N = \sqrt{N_{avg}}\). The resulting \(\sigma_{VT}\):

\[ \sigma_{VT}^{RDF} = \frac{q}{C_{ox}}\frac{\sigma_{Q_{dep}}}{A} = \frac{q}{C_{ox}A}\sqrt{qN_A x_{dmax}/A \cdot A} = \frac{1}{C_{ox}}\sqrt{\frac{q^3 N_A x_{dmax}}{2\varepsilon_s A}} \]

where \(A = WL\) is the channel area. The pelgrom-like scaling \(\sigma_{VT} \propto 1/\sqrt{WL}\) means larger transistors have better matching. The Pelgrom coefficient for a process is \(A_{VT} = \sigma_{VT}\sqrt{WL}\), measured in mV\(\cdot\mu\)m. Typical values: planar bulk 28 nm CMOS: \(A_{VT} \approx 4\;\text{mV}\mu\text{m}\); FinFET: \(A_{VT} \approx 1\;\text{mV}\mu\text{m}\) (due to undoped channel).

Line edge roughness (LER). During lithography and etching, the gate edge is not perfectly straight. The root-mean-square roughness \(\Delta L_{rms}\) of the gate length results in a \(V_T\) variation:

\[ \sigma_{VT}^{LER} = \left|\frac{\partial V_T}{\partial L}\right| \Delta L_{rms} \]

where \(|\partial V_T/\partial L|\) is the short-channel sensitivity of \(V_T\). As devices shrink and SCEs become stronger, LER becomes a more severe contributor to variability.

Oxide thickness fluctuation. Atomic-scale roughness in the gate dielectric causes \(C_{ox}\) to vary:

\[ \sigma_{VT}^{tox} = (V_{GS}-V_T)\frac{\sigma_{tox}}{t_{ox}} \]

For high-\(\kappa\)/metal gate stacks, the dominant variability is often dipole formation at the high-\(\kappa\)/metal interface, characterized by an areal density of dipole scattering centers.

Total \(\sigma_{VT}\) is the quadrature sum of independent contributions:

\[ \sigma_{VT}^{total} = \sqrt{\left(\sigma_{VT}^{RDF}\right)^2 + \left(\sigma_{VT}^{LER}\right)^2 + \left(\sigma_{VT}^{tox}\right)^2 + \cdots} \]

Minimising \(\sigma_{VT}\) is one of the key process integration challenges for SRAM (which requires \(\sigma_{VT} < 30\;\text{mV}\) for reliable 6T SRAM cell operation at low supply voltage).

20.4 Small-Signal Analysis of the Common-Source Amplifier

Consider an NMOS common-source amplifier with source degeneration resistor \(R_S\), drain resistor \(R_D\), and a gate bias through \(R_G\). At mid-band (capacitors are shorts/opens as appropriate), the small-signal equivalent circuit is analysed as follows.

The KCL at the drain node gives:

\[ v_{out} = -I_D R_D = -(g_m v_{gs} + g_{mb}v_{bs})R_D \]

With source degeneration: \(v_{gs} = v_{in} - v_s = v_{in} - I_D R_S\) and \(v_{bs} = -v_s = -I_D R_S\):

\[ I_D = g_m(v_{in} - I_D R_S) - g_{mb}I_D R_S \]\[ I_D(1 + (g_m + g_{mb})R_S) = g_m v_{in} \]\[ I_D = \frac{g_m}{1 + (g_m+g_{mb})R_S} v_{in} \]

The voltage gain:

\[ A_v = \frac{v_{out}}{v_{in}} = -\frac{g_m R_D}{1 + (g_m+g_{mb})R_S} \]

For \(R_S = 0\): \(A_v = -g_m R_D\) (the basic common-source gain). Source degeneration reduces the gain by the factor \(1 + (g_m+g_{mb})R_S\) but improves linearity and increases the input-referred 3 dB bandwidth by approximately the same factor — the classical gain-bandwidth trade-off. The output resistance looking into the drain is:

\[ R_{out} = r_o\left(1 + (g_m + g_{mb})R_S\right) + R_S \]

This increase in output resistance (the source-degenerated cascode effect) is essential for high-gain operational amplifier stages.