These notes synthesize the standard curriculum for ECE 231 at the University of Waterloo as taught by Prof. William S. Wong, following the chapter sequence of Neamen’s Semiconductor Physics and Devices (4th ed.). They are written as a self-contained textbook: every major result is derived from first principles, every equation is motivated physically before it is written down, and every device chapter closes with a worked example that ties together the theory.

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Sources and References

• D. A. Neamen, Semiconductor Physics and Devices: Basic Principles, 4th ed. (McGraw-Hill, 2012). Primary reference for this course; equation numbering and chapter structure follow this text.
• B. G. Streetman and S. K. Banerjee, Solid State Electronic Devices, 7th ed. (Pearson, 2014). Complementary physical intuition, especially for optical devices and band structure.
• R. F. Pierret, Semiconductor Device Fundamentals (Addison-Wesley, 1996). Rigorous derivations of junction and MOSFET equations, excellent worked examples.
• MIT OpenCourseWare 6.012, Microelectronic Devices and Circuits (open lecture notes, freely available). Clear derivations of MOS capacitor physics and quasi-Fermi level formalism.
• M. S. Lundstrom, nanoHUB lectures, Fundamentals of Carrier Transport, 2nd ed. (Purdue University, freely available). Modern, rigorous treatment of drift–diffusion, effective mass, and high-field transport.
• S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, 3rd ed. (Wiley, 2007). Advanced reference for Schottky contacts, breakdown, and high-frequency device physics.
• M. Lundstrom and J. Guo, Nanoscale Transistors: Device Physics, Modeling, and Simulation (Springer, 2006). Short-channel effects, velocity saturation, and ballistic transport.

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Chapter 1: Crystal Structure of Solids

1.1 The Solid State and Why It Matters

A semiconductor device is, at its core, a piece of crystalline solid whose electrical properties have been sculpted by chemistry and geometry. Before we can understand why silicon conducts poorly in the dark and well in the light, or why adding a trace of phosphorus changes its resistivity by seven orders of magnitude, we need a precise vocabulary for the arrangement of atoms in space.

Solids are classified by the degree of order in their atomic arrangement. Amorphous solids (glass, amorphous silicon) have no long-range periodicity. Polycrystalline solids are mosaics of small single-crystal grains separated by grain boundaries. Single-crystal (monocrystalline) solids exhibit a perfectly repeating atomic arrangement throughout their entire macroscopic volume. Nearly all semiconductor devices of practical importance — silicon integrated circuits, III–V lasers, GaN power transistors — are fabricated in single-crystal material, because only the single crystal permits precise control of electronic band structure and carrier transport.

The periodic arrangement of atoms in a crystal is described mathematically by the direct lattice and its associated reciprocal lattice, which together encode the translational symmetry that underlies the entire band theory of solids.

1.2 Bravais Lattices and the Unit Cell

There are exactly fourteen distinct Bravais lattice types in three dimensions, grouped into seven crystal systems (cubic, tetragonal, orthorhombic, hexagonal, trigonal, monoclinic, triclinic). For semiconductor physics the cubic system dominates: simple cubic (SC), body-centred cubic (BCC), and face-centred cubic (FCC).

The conventional unit cell of the FCC lattice is a cube of side \(a\) (the lattice constant) with atoms at each corner and at the centre of each face. Each corner atom is shared by eight unit cells, contributing \(\tfrac{1}{8}\) of an atom; each face atom is shared by two cells, contributing \(\tfrac{1}{2}\). The total number of atoms per conventional FCC cell is therefore

\[ 8 \times \tfrac{1}{8} + 6 \times \tfrac{1}{2} = 4. \]

The FCC primitive cell — the smallest volume that, when periodically repeated, tiles all of space — is a rhombohedron containing exactly one lattice point. The Wigner–Seitz cell is the most symmetrical primitive cell: the region of space closer to one lattice point than to any other. For the FCC lattice, the Wigner–Seitz cell is a truncated octahedron; its counterpart in reciprocal space is the first Brillouin zone, which for FCC is an truncated octahedron and for BCC is a rhombic dodecahedron.

1.3 The Diamond and Zincblende Structures

Silicon and germanium crystallise in the diamond cubic structure: an FCC lattice with a two-atom basis. The two atoms of the basis are located at \((0,0,0)\) and \(\bigl(\tfrac{a}{4}, \tfrac{a}{4}, \tfrac{a}{4}\bigr)\) in Cartesian coordinates. Equivalently, the diamond structure is two interpenetrating FCC sublattices, displaced relative to one another by \(\tfrac{a}{4}(1,1,1)\). Each atom is tetrahedrally bonded to four nearest neighbours, consistent with the \(sp^3\) hybrid orbital chemistry of group-IV elements.

The diamond structure has eight atoms per conventional cubic cell. The number of nearest neighbours (coordination number) is 4. The nearest-neighbour distance is \(d = \tfrac{\sqrt{3}}{4}a\). The second-nearest-neighbour distance is \(\tfrac{a}{\sqrt{2}}\) and there are twelve such neighbours, forming a shell of FCC-like arrangement.

Important III–V and II–VI compound semiconductors that adopt the zincblende structure include GaAs, InP, InAs, GaP, AlAs, ZnS, and CdTe. The polar character of the bonds (partial ionic character due to differing electronegativities) gives rise to piezoelectric effects not present in the elemental semiconductors. Additionally, GaN and other nitrides adopt the wurtzite structure (a hexagonal analogue of zincblende), which exhibits large spontaneous and piezoelectric polarisations exploited in AlGaN/GaN high-electron-mobility transistors (HEMTs).

1.4 Miller Indices and Crystal Planes

Planes and directions in a crystal are described by Miller indices, a compact integer notation derived from the intercepts of the plane with the three crystallographic axes.

The three most important planes in silicon technology are (100), (110), and (111). Silicon wafers for CMOS are typically cut with the (100) surface exposed, because this orientation gives the lowest interface state density at the Si–SiO\(_2\) interface and the highest electron mobility in the inversion layer. The (111) plane has the highest packing density and is relevant for bipolar devices and heteroepitaxial growth. The \(\langle 110 \rangle\) directions are the slip directions in silicon and set the mechanical cleavage planes, which is why silicon wafers have a flat or notch aligned to \(\langle 110 \rangle\) for orientation reference.

The atomic planar density of a \((hkl)\) surface determines properties such as surface energy, step density during growth, and oxide quality. The (100) silicon surface has a planar density of \(2/a^2 = 6.78 \times 10^{14}\) cm\(^{-2}\), while (111) has \(4/(\sqrt{3}a^2) = 7.83 \times 10^{14}\) cm\(^{-2}\).

1.5 Atomic Packing and the Lattice Constant of Silicon

For silicon, the lattice constant at room temperature is \(a = 5.431\) Å \(= 0.5431\) nm. The nearest-neighbour Si–Si bond length is

\[ d = \frac{\sqrt{3}}{4}a = \frac{\sqrt{3}}{4}(5.431) = 2.352 \text{ Å}, \]

consistent with twice the covalent radius of silicon (\(r_{cov} \approx 1.17\) Å). The atomic packing fraction of the diamond structure is

\[ \text{APF} = \frac{8 \times \tfrac{4}{3}\pi r^3}{a^3} = \frac{8 \times \tfrac{4}{3}\pi \left(\tfrac{\sqrt{3}}{8}a\right)^3}{a^3} = \frac{\pi\sqrt{3}}{16} \approx 0.340. \]

This is considerably lower than for FCC metals (\(\approx 0.740\)), reflecting the open tetrahedral bonding geometry required by the directional covalent \(sp^3\) bonds. The low packing fraction means the diamond lattice has significant interstitial space — important for dopant diffusion during thermal processing, where interstitial diffusion mechanisms dominate over substitutional ones for many dopants.

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Chapter 2: Quantum Theory of Solids

2.1 From Atomic Orbitals to Energy Bands

The electronic structure of an isolated atom consists of discrete energy levels. When \(N\) atoms are brought together to form a crystal, the Pauli exclusion principle demands that no two electrons occupy the same quantum state. What was a single atomic energy level splits into a quasi-continuous band of \(N\) closely-spaced levels. In the limit \(N \to 10^{23}\) (Avogadro scale), the splitting is so dense that the band is treated as a continuum.

Consider the \(3s\) level of silicon: isolated Si has a sharp \(3s\) level at \(-14.9\) eV. In crystalline silicon, this level broadens into a band. The \(3p\) levels do the same. At sufficiently small inter-atomic separations, the \(3s\) and \(3p\)-derived bands hybridise (as do the atomic wavefunctions in \(sp^3\) bonding), producing a bonding band (valence band) and an anti-bonding band (conduction band) separated by the band gap.

The central insight is this: the discrete energy spectrum of atoms becomes the band structure of solids. Regions of allowed electron energies are called energy bands; gaps between them are called band gaps or forbidden gaps.

2.2 Bloch’s Theorem

The crystal momentum \(\hbar\mathbf{k}\) plays the role of momentum but is defined only modulo a reciprocal lattice vector \(\mathbf{G}\): states with \(\mathbf{k}\) and \(\mathbf{k} + \mathbf{G}\) are physically identical. This means all distinct \(\mathbf{k}\) values can be taken within the first Brillouin zone.

Bloch’s theorem is not an approximation: it is an exact consequence of the translational symmetry of a perfectly periodic potential. Real crystals have broken periodicity at surfaces, at defects, and due to thermal disorder (phonons) — but over length scales of many unit cells, Bloch states remain excellent approximations.

2.3 The Kronig–Penney Model and Band Gaps

The most instructive simple model for band formation is the Kronig–Penney model: an electron moving in a one-dimensional periodic square-wave potential

\[ V(x) = \begin{cases} 0, & 0 < x < a \\ V_0, & -b < x < 0 \end{cases} \]

with period \(d = a + b\). Solving the Schrödinger equation in each region and applying Bloch boundary conditions at the interfaces leads to the transcendental equation

\[ \cos(kd) = \cos(\alpha a)\cos(\beta b) - \frac{\alpha^2 + \beta^2}{2\alpha\beta}\sin(\alpha a)\sin(\beta b), \]

where \(\alpha = \sqrt{2mE}/\hbar\) in the well and \(\beta = \sqrt{2m(V_0-E)}/\hbar\) in the barrier (for \(E < V_0\)). Because \(|\cos(kd)| \leq 1\), energies for which the right-hand side exceeds unity are forbidden. These forbidden ranges are the band gaps.

Taking the limit of delta-function barriers (\(V_0 \to \infty\), \(b \to 0\) with \(V_0 b \equiv P\hbar^2/ma\) fixed) simplifies the equation to the often-quoted form:

\[ \cos(ka) = \frac{P\sin(\alpha a)}{\alpha a} + \cos(\alpha a). \]

The parameter \(P\) controls the strength of the periodic potential: \(P = 0\) (no potential) gives \(k = \alpha\) (free electron parabola); large \(P\) produces wide band gaps and narrow bands (nearly atomic limit).

2.4 Effective Mass and the \(E\)–\(k\) Diagram

Near the band edges, the \(E\)–\(k\) dispersion is approximately parabolic:

\[ E(\mathbf{k}) \approx E_c + \frac{\hbar^2 k^2}{2m^*_n} \]

for the conduction band minimum, and

\[ E(\mathbf{k}) \approx E_v - \frac{\hbar^2 k^2}{2m^*_p} \]

for the valence band maximum.

A sharply curved (wide) band gives a small effective mass and high mobility; a flat band gives a large effective mass and sluggish response. For silicon, the conduction band minimum is at \(\approx 0.85\times(2\pi/a)\) along \(\langle 100 \rangle\), and there are six equivalent valleys. Each valley is ellipsoidal: longitudinal effective mass \(m_l^* = 0.916\, m_0\), transverse \(m_t^* = 0.190\, m_0\). The density-of-states effective mass averages over all six valleys:

\[ m^*_{n,dos} = 6^{2/3}(m_l^* m_t^{*2})^{1/3} \approx 1.08\, m_0 \quad \text{(DOS effective mass)}, \]

while the conductivity effective mass (relevant for transport) is:

\[ \frac{1}{m^*_{n,c}} = \frac{1}{3}\left(\frac{1}{m_l^*} + \frac{2}{m_t^*}\right) \implies m^*_{n,c} \approx 0.26\, m_0. \]

The valence band of silicon has a more complex structure: heavy holes (HH), light holes (LH), and split-off (SO) bands all meet at \(\Gamma\). The density-of-states effective mass for holes is \(m^*_p \approx 0.386\, m_0\). For GaAs, \(m^*_n \approx 0.067\, m_0\) — the low mass arises from the strongly \(s\)-like conduction band, and is the reason GaAs electron mobilities (\(\mu_n \approx 8500\) cm\(^2\)/V·s) far exceed silicon’s.

2.5 Direct and Indirect Band Gaps

GaAs is a direct-gap semiconductor with \(E_g = 1.42\) eV at 300 K, with both extrema at \(k = 0\) (the \(\Gamma\) point). Silicon is an indirect-gap semiconductor with \(E_g = 1.12\) eV at 300 K: the valence band maximum is at \(\Gamma\), but the conduction band minimum is near the \(X\) point along \(\langle 100 \rangle\).

A band-to-band optical transition requires conservation of both energy and momentum. A photon carries negligible momentum compared with a phonon. In a direct-gap material, an electron near the conduction band minimum can recombine directly with a hole near the valence band maximum by emitting a photon — no additional momentum is required. In an indirect-gap material, the momentum mismatch must be supplied by a phonon (a quantised lattice vibration), making radiative recombination far less probable. Quantitatively, the ratio of radiative recombination coefficients \(B\) is roughly \(B_{GaAs}/B_{Si} \sim 10^4\). This is why silicon LEDs and silicon lasers are extraordinarily difficult to realise, while GaAs and InGaN LEDs are efficient.

The temperature dependence of the band gap is given empirically by the Varshni formula:

\[ E_g(T) = E_g(0) - \frac{\alpha T^2}{T + \beta}, \]

where \(\alpha\) and \(\beta\) are material-specific constants. For silicon: \(E_g(0) = 1.170\) eV, \(\alpha = 4.73\times10^{-4}\) eV/K, \(\beta = 636\) K, giving \(E_g(300\text{ K}) = 1.12\) eV. The decrease of \(E_g\) with temperature arises from lattice dilation and electron–phonon coupling. It has important consequences for device operation at elevated temperatures.

2.6 Density of States

The density of states \(g(E)\) is the number of electron states per unit volume per unit energy at energy \(E\). For a three-dimensional parabolic band with effective mass \(m^*\):

\[ g_c(E) = \frac{4\pi (2m^*_{n,dos})^{3/2}}{h^3} \sqrt{E - E_c}, \qquad E \geq E_c, \]\[ g_v(E) = \frac{4\pi (2m^*_{p,dos})^{3/2}}{h^3} \sqrt{E_v - E}, \qquad E \leq E_v. \]

These expressions follow from counting the number of allowed \(\mathbf{k}\)-states in a spherical shell of radius \(k\) and thickness \(dk\) in reciprocal space (with density \(1/(2\pi)^3\) per unit volume), converting to energy via the parabolic dispersion, and multiplying by 2 for spin. For silicon’s six-valley conduction band, the calculation replaces the free-electron mass with the DOS effective mass, which already accounts for valley degeneracy. The resulting density of states rises monotonically above \(E_c\), providing the large pool of states that can be populated by injection or thermal excitation.

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Chapter 3: Semiconductors in Equilibrium

3.1 The Fermi–Dirac Distribution

The probability that an electron occupies a quantum state of energy \(E\) at temperature \(T\) is given by the Fermi–Dirac distribution:

\[ f(E) = \frac{1}{1 + \exp\!\left(\dfrac{E - E_F}{k_B T}\right)}, \]

where \(E_F\) is the Fermi energy (or Fermi level) and \(k_B = 8.617 \times 10^{-5}\) eV/K is Boltzmann’s constant. At absolute zero, \(f(E) = 1\) for all \(E < E_F\) and \(f(E) = 0\) for all \(E > E_F\): the Fermi level divides filled from empty states. At finite temperature, the distribution is smeared over a range of order \(k_B T\) around \(E_F\).

The probability that a state is empty (occupied by a hole) is:

\[ 1 - f(E) = \frac{1}{1 + \exp\!\left(\dfrac{E_F - E}{k_BT}\right)}. \]

For states well above \(E_F\) — specifically, for \(E - E_F \gg k_B T\) — the Fermi–Dirac distribution is well approximated by the Boltzmann factor:

\[ f(E) \approx \exp\!\left(-\frac{E - E_F}{k_B T}\right) \qquad \text{(Boltzmann approximation)}. \]

This approximation holds for non-degenerate semiconductors, where \(E_F\) lies more than about \(3k_BT\) below the conduction band edge (or above the valence band edge). The error introduced is less than 5% when \(E_c - E_F \geq 3k_BT \approx 78\) meV at 300 K.

3.2 Carrier Concentrations and Effective Density of States

The electron concentration in the conduction band is obtained by integrating the product of the density of states and the Fermi–Dirac distribution:

\[ n_0 = \int_{E_c}^{\infty} g_c(E)\, f(E)\, dE. \]

Under the Boltzmann approximation, this integral evaluates to

\[ n_0 = N_c \exp\!\left(-\frac{E_c - E_F}{k_B T}\right), \]

where the effective density of states in the conduction band is

\[ N_c = 2\left(\frac{2\pi m^*_{n,dos} k_B T}{h^2}\right)^{3/2}. \]

Similarly, the hole concentration in the valence band is

\[ p_0 = N_v \exp\!\left(-\frac{E_F - E_v}{k_B T}\right), \]

where the effective density of states in the valence band is

\[ N_v = 2\left(\frac{2\pi m^*_{p,dos} k_B T}{h^2}\right)^{3/2}. \]

At 300 K, for silicon: \(N_c = 2.8 \times 10^{19}\) cm\(^{-3}\) and \(N_v = 1.04 \times 10^{19}\) cm\(^{-3}\). The \(N_c\) and \(N_v\) values scale as \(T^{3/2}\), which is the single most important temperature dependence in semiconductor physics — it drives the exponential increase in \(n_i\) with temperature.

When \(E_F\) approaches or enters the band (degenerate doping, \(N_d \gtrsim N_c\)), the Boltzmann approximation fails and the full Fermi–Dirac integral must be used:

\[ n_0 = \frac{2}{\sqrt{\pi}} N_c \mathcal{F}_{1/2}\!\left(\frac{E_F - E_c}{k_BT}\right), \]

where \(\mathcal{F}_{1/2}(\eta) = \int_0^\infty \sqrt{u}/(1+e^{u-\eta})\, du\) is the Fermi–Dirac integral of order 1/2. For very heavily doped silicon (\(N_d > 10^{19}\) cm\(^{-3}\)), band-gap narrowing and carrier degeneracy both become important and must be treated self-consistently.

3.3 The Intrinsic Semiconductor and the Mass-Action Law

Multiplying the expressions for \(n_0\) and \(p_0\):

\[ n_0 p_0 = N_c N_v \exp\!\left(-\frac{E_c - E_v}{k_BT}\right) = N_c N_v \exp\!\left(-\frac{E_g}{k_BT}\right) \equiv n_i^2. \]

This is the mass-action law. It is a consequence of thermodynamic equilibrium and holds regardless of doping, provided the semiconductor remains non-degenerate and in thermal equilibrium. At 300 K, \(n_i \approx 1.5 \times 10^{10}\) cm\(^{-3}\) for silicon. For germanium (\(E_g = 0.66\) eV), \(n_i \approx 2.4 \times 10^{13}\) cm\(^{-3}\) — a consequence of the smaller band gap. For GaAs (\(E_g = 1.42\) eV), \(n_i \approx 2 \times 10^6\) cm\(^{-3}\) — so intrinsic GaAs is far more insulating than intrinsic silicon.

Setting \(n_0 = p_0 = n_i\) and solving for the intrinsic Fermi level \(E_i\):

\[ E_i = \frac{E_c + E_v}{2} + \frac{k_BT}{2}\ln\!\left(\frac{N_v}{N_c}\right) = \frac{E_c + E_v}{2} + \frac{3k_BT}{4}\ln\!\left(\frac{m^*_p}{m^*_n}\right). \]

For silicon, \(E_i\) lies slightly below the midgap energy because \(m^*_p > m^*_n\). The correction is only \(\approx 13\) meV at 300 K, so \(E_i\) is conventionally taken as the midgap reference. Using \(E_i\) as a reference, the equilibrium concentrations take the transparent form:

\[ n_0 = n_i \exp\!\left(\frac{E_F - E_i}{k_BT}\right), \qquad p_0 = n_i \exp\!\left(\frac{E_i - E_F}{k_BT}\right). \]

These equations show elegantly that \(n_0 > n_i\) when \(E_F > E_i\) (n-type), and \(p_0 > n_i\) when \(E_F < E_i\) (p-type).

3.4 Extrinsic Semiconductors: Doping

Controlled introduction of impurity atoms — a process called doping — shifts the Fermi level and dramatically alters carrier concentrations. This is the central engineering degree of freedom in all semiconductor devices.

In silicon, group-V elements (phosphorus, arsenic, antimony) act as donors. A phosphorus atom substituting for silicon contributes four of its five valence electrons to covalent bonds; the fifth is weakly bound to the phosphorus core in a hydrogen-like orbit. The binding energy is estimated by the hydrogen model scaled by the effective mass and dielectric constant:

\[ E_d = \frac{m^*_n e^4}{2(4\pi\varepsilon_s\hbar)^2} = \frac{m^*_n}{m_0\varepsilon_r^2}\times 13.6 \text{ eV} \approx \frac{0.26}{(11.7)^2}\times 13.6 \approx 25 \text{ meV}. \]

The actual ionisation energies (45 meV for P, 54 meV for As, 39 meV for Sb) are somewhat larger due to central-cell corrections, but all are far smaller than \(E_g = 1.12\) eV. At room temperature (\(k_BT \approx 26\) meV), essentially all donors are ionised — the complete ionisation approximation.

Under complete ionisation, the charge neutrality condition is:

\[ n_0 + N_a = p_0 + N_d. \]

For a compensated n-type semiconductor with both donors and acceptors, combining charge neutrality with the mass-action law \(n_0 p_0 = n_i^2\):

\[ n_0 = \frac{(N_d - N_a)}{2} + \sqrt{\left(\frac{N_d - N_a}{2}\right)^2 + n_i^2}. \]

When \(N_d - N_a \gg n_i\) (strongly extrinsic, the common practical case):

\[ n_0 \approx N_d - N_a, \qquad p_0 \approx \frac{n_i^2}{N_d - N_a}. \]

The Fermi level in n-type silicon:

\[ E_F = E_c - k_BT\ln\!\left(\frac{N_c}{n_0}\right) = E_i + k_BT\ln\!\left(\frac{n_0}{n_i}\right). \]

Doping silicon to \(N_d = 10^{16}\) cm\(^{-3}\) places \(E_F\) approximately \(k_BT\ln(10^{16}/1.5\times10^{10}) \approx 0.347\) eV above \(E_i\), and the minority carrier concentration drops to \(p_0 = n_i^2/N_d = (1.5\times10^{10})^2/10^{16} = 2.25\times10^4\) cm\(^{-3}\) — more than five orders of magnitude below the majority concentration. This extreme asymmetry between majority and minority concentrations underlies the rectifying behaviour of all p–n junctions.

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Chapter 4: Carrier Transport Phenomena

4.1 Drift and Mobility

When an electric field \(\mathcal{E}\) is applied to a semiconductor, free carriers are accelerated. Between scattering events, an electron gains momentum from the field. Scattering — from phonons, ionised impurities, and defects — randomises the momentum. In steady state, the average drift velocity of electrons is:

\[ v_{d,n} = -\mu_n \mathcal{E}, \qquad v_{d,p} = +\mu_p \mathcal{E}, \]

where the mobility is \(\mu = e\tau/m^*\), with \(\tau\) the momentum relaxation time.

In silicon at 300 K under low-field conditions: \(\mu_n \approx 1350\) cm\(^2\)/V·s and \(\mu_p \approx 480\) cm\(^2\)/V·s. In GaAs: \(\mu_n \approx 8500\) cm\(^2\)/V·s, \(\mu_p \approx 400\) cm\(^2\)/V·s. The high GaAs electron mobility reflects the small effective mass \(m^*_n = 0.067\, m_0\): since \(\mu = e\tau/m^*\) and the phonon scattering time \(\tau\) is similar in both materials, the lower mass gives proportionally higher mobility.

Mobility decreases with increasing doping because ionised impurities act as Coulomb scattering centres. Empirical models (Masetti, Caughey–Thomas) describe this accurately. For phosphorus-doped silicon, the electron mobility falls from \(\approx 1350\) cm\(^2\)/V·s at \(N_d = 10^{14}\) cm\(^{-3}\) to \(\approx 90\) cm\(^2\)/V·s at \(N_d = 10^{20}\) cm\(^{-3}\).

The principal scattering mechanisms are:

• Lattice (acoustic phonon) scattering: \(\mu_L \propto T^{-3/2}\). Dominates at room temperature and moderate doping.
• Ionised impurity scattering: \(\mu_I \propto T^{3/2}/N_{imp}\). Dominates at low temperature or high doping.
• Optical phonon scattering: important in polar III–V materials (GaAs) at high fields.

Matthiessen’s rule gives the combined mobility:

\[ \frac{1}{\mu} = \frac{1}{\mu_L} + \frac{1}{\mu_I} + \cdots \]

4.2 Conductivity and Resistivity

The drift current density due to both carrier types is:

\[ J_{drift} = e n_0 v_{d,n} - e p_0 v_{d,p}= (e n_0\mu_n + e p_0\mu_p)\mathcal{E} = \sigma \mathcal{E}, \]

where \(\sigma = e(n_0\mu_n + p_0\mu_p)\) is the electrical conductivity. The resistivity is \(\rho = 1/\sigma\). For an n-type semiconductor with \(n_0 \gg p_0\):

\[ \rho \approx \frac{1}{e n_0\mu_n}. \]

For example, silicon doped to \(N_d = 10^{16}\) cm\(^{-3}\) has \(\rho \approx 1/(1.6\times10^{-19}\times10^{16}\times1350) \approx 0.46\) \(\Omega\)·cm. This formula underlies the use of four-point probe measurements to characterise wafer doping uniformity.

4.3 Velocity Saturation at High Fields

At high electric fields (\(\mathcal{E} \gtrsim 10^4\) V/cm in silicon), the drift velocity no longer increases linearly with field. Carriers gain enough energy to emit optical phonons efficiently, and the drift velocity approaches a saturation velocity \(v_{sat}\). For silicon, \(v_{sat} \approx 10^7\) cm/s for both electrons and holes at 300 K.

A widely-used empirical model for electrons in silicon is:

\[ v_d = \frac{\mu_n \mathcal{E}}{\left[1 + \left(\dfrac{\mu_n \mathcal{E}}{v_{sat}}\right)^2\right]^{1/2}}. \]

Velocity saturation limits the maximum current in short-channel MOSFETs and is a critical design constraint in modern VLSI. In deeply scaled transistors with channel lengths below 10 nm, carriers traverse the channel nearly ballistically and the effective velocity can momentarily exceed \(v_{sat}\) by a factor of 2–3 before scattering occurs.

4.4 Diffusion and the Einstein Relation

Carriers also move in response to concentration gradients — this is diffusion. The diffusion current density is given by Fick’s first law:

\[ J_{n,diff} = eD_n \frac{dn}{dx}, \qquad J_{p,diff} = -eD_p \frac{dp}{dx}. \]

The sign convention: electrons diffuse from high to low concentration, but because their charge is negative, the resulting current flows up the concentration gradient; holes diffuse toward low concentration and their positive charge makes the current flow in the direction of diffusion.

At thermal equilibrium, there can be no net current. This constraint, applied to the total current (drift plus diffusion), requires that the drift and diffusion currents exactly cancel. From this condition one derives the Einstein relation:

Derivation. In equilibrium, the total electron current is zero:

\[ 0 = J_n = e\mu_n n_0 \mathcal{E} + eD_n \frac{dn_0}{dx}. \]

Using \(\mathcal{E} = -(1/e)dE_i/dx\) and \(n_0 = n_i\exp[(E_F - E_i)/k_BT]\) with constant \(E_F\):

\[ \frac{dn_0}{dx} = \frac{n_0}{k_BT}\left(-\frac{dE_i}{dx}\right) = \frac{en_0}{k_BT}\mathcal{E}. \]

Substituting: \(0 = e\mu_n n_0\mathcal{E} + eD_n(en_0/k_BT)\mathcal{E}\), which gives \(D_n = k_BT\mu_n/e\). \(\square\)

For silicon at 300 K: \(D_n = (0.02585)(1350) \approx 34.9\) cm\(^2\)/s and \(D_p = (0.02585)(480) \approx 12.4\) cm\(^2\)/s. The Einstein relation is the bridge between diffusion and mobility: one need only measure one to know the other.

4.5 The Hall Effect

The Hall effect provides a direct experimental measurement of carrier type, carrier concentration, and mobility. When a current \(I_x\) flows in the \(x\)-direction and a magnetic field \(B_z\) is applied in the \(z\)-direction, the Lorentz force \(\mathbf{F} = q\mathbf{v}\times\mathbf{B}\) deflects carriers in the \(y\)-direction. Charge accumulates until the resulting transverse Hall field \(\mathcal{E}_y\) balances the Lorentz force:

\[ e\mathcal{E}_y = ev_{d,x}B_z \implies \mathcal{E}_y = v_{d,x}B_z = \frac{J_x B_z}{en_0}. \]

The Hall coefficient is:

\[ R_H = \frac{\mathcal{E}_y}{J_x B_z} = \begin{cases} -1/(en_0) & \text{n-type} \\ +1/(ep_0) & \text{p-type.} \end{cases} \]

The sign of \(R_H\) identifies carrier type; its magnitude gives carrier concentration. The Hall mobility is \(\mu_H = |R_H|\sigma\), which is close to (but not exactly equal to) the drift mobility \(\mu\) due to the Hall scattering factor \(r_H = \mu_H/\mu \approx 1\) for typical semiconductors.

The Haynes–Shockley experiment uses a similar geometry to measure the minority carrier drift mobility, diffusivity, and lifetime simultaneously, complementing Hall measurements that probe majority carriers.

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Chapter 5: Non-Equilibrium Excess Carriers

5.1 Generation and Recombination Mechanisms

In equilibrium, generation and recombination are equal and opposite. Any disturbance creates excess carriers: \(\delta n = n - n_0\) and \(\delta p = p - p_0\). Charge neutrality of the bulk (space charge relaxes on the dielectric relaxation timescale \(\tau_d = \varepsilon/\sigma \sim 10^{-12}\) s in silicon) requires \(\delta n = \delta p\).

Three primary recombination mechanisms operate:

Band-to-band (direct) recombination. An electron falls directly from conduction to valence band, emitting a photon (or, rarely, a phonon). Rate per unit volume: \(R = Bnp\), where \(B \approx 10^{-10}\) cm\(^3\)/s for GaAs and \(B \approx 10^{-14}\) cm\(^3\)/s for silicon. The net recombination rate is \(U = B(np - n_i^2)\).

Shockley–Read–Hall (SRH) recombination. In indirect-gap semiconductors, deep-level traps at energy \(E_t\) near midgap mediate recombination. An electron is first captured by a trap (at rate \(v_{th}\sigma_n N_t n\)); the trap then captures a hole (at rate \(v_{th}\sigma_p N_t p\)), completing the recombination event. The net recombination rate is:

\[ U_{SRH} = \frac{np - n_i^2}{\tau_p(n + n_1) + \tau_n(p + p_1)}, \]

where \(n_1 = n_i e^{(E_t - E_i)/k_BT}\), \(p_1 = n_i e^{(E_i - E_t)/k_BT}\), and \(\tau_{n,p} = 1/(v_{th}\sigma_{n,p} N_t)\). Traps at midgap maximise \(U_{SRH}\) and are the most recombination-active. Common mid-gap traps in silicon include Au, Fe, and certain transition metals — which is why these metals must be kept out of silicon device fabrication areas.

Auger recombination. An electron–hole pair recombines and the energy is transferred to a third carrier, which thermalises. Rates scale as \(C_n n^2 p + C_p np^2\), where \(C_n \approx C_p \approx 10^{-30}\) cm\(^6\)/s for silicon. Auger dominates at \(n \gtrsim 10^{18}\) cm\(^{-3}\) and limits the performance of heavily doped emitters in BJTs and solar cells.

5.2 Low-Injection Minority Carrier Lifetime

For small excess carrier concentrations injected into p-type material (\(\delta n \ll p_0\), the low-injection limit), the SRH rate simplifies to:

\[ U_{SRH} \approx \frac{\delta n}{\tau_n}, \]

where the minority carrier electron lifetime \(\tau_n = 1/(v_{th}\sigma_n N_t)\) is independent of carrier concentration. Similarly in n-type material, \(U \approx \delta p/\tau_p\).

Typical minority carrier lifetimes in silicon:

• Float-zone (very pure) silicon: \(\tau \sim 1\) ms
• Czochralski silicon (standard IC substrate): \(\tau \sim 10\)–\(100\) μs
• Heavily doped (\(N > 10^{18}\) cm\(^{-3}\)): \(\tau \sim 1\)–\(100\) ns due to Auger dominance

The minority carrier lifetime is one of the most important parameters in solar cell and photodetector design, directly setting the collection efficiency for photogenerated carriers.

5.3 The Continuity Equations

Conservation of carriers combined with drift–diffusion transport gives:

\[ \frac{\partial n}{\partial t} = G_n - U_n + \frac{1}{e}\frac{\partial J_n}{\partial x}, \]\[ \frac{\partial p}{\partial t} = G_p - U_p - \frac{1}{e}\frac{\partial J_p}{\partial x}. \]

Substituting the full drift–diffusion expressions \(J_n = e\mu_n n\mathcal{E} + eD_n\partial n/\partial x\) and \(J_p = e\mu_p p\mathcal{E} - eD_p\partial p/\partial x\), and subtracting the equilibrium concentrations to focus on excess carriers, one arrives at the minority carrier diffusion equations.

5.4 Minority Carrier Diffusion Equations and Diffusion Length

Under low injection, uniform doping, zero applied field, steady state, and with a constant uniform optical generation rate \(G_{op}\):

\[ D_n \frac{d^2(\delta n)}{dx^2} - \frac{\delta n}{\tau_n} + G_{op} = 0 \qquad \text{(minority electrons in p-type)}. \]

In the dark (\(G_{op} = 0\)), the general solution is:

\[ \delta n(x) = A e^{x/L_n} + B e^{-x/L_n}, \]

where the minority carrier diffusion length is:

\[ L_n = \sqrt{D_n \tau_n}. \]

For silicon with \(D_n = 25\) cm\(^2\)/s and \(\tau_n = 10\) μs, \(L_n \approx 0.5\) mm. This is much larger than a typical device dimension, which is why minority carrier transport can be efficient across the thin bases of bipolar transistors. Uniform illumination (\(G_{op} = \text{const}\)) adds a particular solution \(\delta n_{steady} = G_{op}\tau_n\), giving a flat offset on top of the transient solution.

5.5 Surface Recombination and the Haynes–Shockley Experiment

Semiconductor surfaces are disordered relative to the bulk crystal: dangling bonds at the surface create a continuous distribution of trap states within the band gap. These surface traps greatly accelerate recombination. The surface recombination rate per unit area is:

\[ U_s = s\, \delta n_s, \]

where \(s\) (cm/s) is the surface recombination velocity and \(\delta n_s\) is the excess minority carrier concentration at the surface. Values of \(s\) range from \(< 1\) cm/s (thermally passivated Si–SiO\(_2\) interface) to \(> 10^6\) cm/s (bare, unpassivated silicon surface). Surface passivation — by thermal oxidation, by hydrogen termination, by Al\(_2\)O\(_3\) atomic-layer deposition — is critical in solar cells, where carriers photogenerated near the surface must reach the junction without recombining.

The surface recombination velocity enters the minority carrier diffusion problem as a boundary condition. For a semi-infinite p-type sample with surface at \(x = 0\) and a source of uniform generation \(G_{op}\), the minority electron current at the surface satisfies:

\[ D_n\frac{d(\delta n)}{dx}\bigg|_{x=0} = s\,\delta n(0). \]

For \(s \to 0\) (perfectly passivated surface), this gives \(d(\delta n)/dx|_{x=0} = 0\) — zero flux out of the surface. For \(s \to \infty\) (ohmic contact, perfect sink), \(\delta n(0) = 0\) — minority carriers are immediately extracted at the surface.

The Haynes–Shockley experiment directly measures minority carrier drift mobility, diffusivity, and lifetime in a bar of semiconductor. A pulse of excess minority carriers (holes in n-type) is injected at point A by a light pulse or a forward-biased point contact. A collecting contact at point B, a distance \(d\) away, detects the pulse. With an electric field \(\mathcal{E}_0\) applied along the bar, the minority carrier pulse drifts toward B at velocity \(v_d = \mu_p \mathcal{E}_0\), while simultaneously spreading by diffusion and decaying by recombination. The pulse shape at B is a Gaussian:

\[ \delta p(d, t) = \frac{\Delta p_0}{\sqrt{4\pi D_p t}}\exp\!\left(-\frac{(d - \mu_p\mathcal{E}_0 t)^2}{4D_p t}\right)\exp\!\left(-\frac{t}{\tau_p}\right). \]

From the time-of-flight \(t_0 = d/(\mu_p\mathcal{E}_0)\), one extracts \(\mu_p\); from the width \(\sigma^2 = 2D_p t_0\) of the Gaussian, one extracts \(D_p\); from the peak amplitude decaying as \(e^{-t_0/\tau_p}\) relative to a reference, one extracts \(\tau_p\). The Haynes–Shockley experiment historically provided the first direct measurements of minority carrier mobility in germanium in the early 1950s, confirming that minority carrier mobility equals majority carrier mobility in the same material (a non-trivial result — it follows from the fact that mobility is set by the semiconductor’s band structure and scattering, not by the carrier’s status as majority or minority).

5.6 Quasi-Fermi Levels and the Demarcation of Equilibrium

Under non-equilibrium conditions, separate quasi-Fermi levels \(E_{Fn}\) and \(E_{Fp}\) are defined for electrons and holes via:

\[ n = n_i\exp\!\left(\frac{E_{Fn} - E_i}{k_BT}\right), \qquad p = n_i\exp\!\left(\frac{E_{Fp} - E_i}{k_BT}\right). \]

In equilibrium, \(E_{Fn} = E_{Fp} = E_F\). The total current densities are then:

\[ J_n = \mu_n n\frac{dE_{Fn}}{dx}, \qquad J_p = \mu_p p\frac{dE_{Fp}}{dx}. \]

This compact form shows that current flows only when a quasi-Fermi level varies spatially. In the quasi-neutral bulk regions far from a junction, with low injection, \(E_{Fn}\) and \(E_{Fp}\) are both approximately flat. Near a forward-biased junction, the quasi-Fermi levels split: \(E_{Fn} - E_{Fp} = eV_A\), where \(V_A\) is the applied forward voltage. This splitting drives minority carrier injection and is the microscopic origin of diode rectification.

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Chapter 6: The p–n Junction

6.1 Formation of the Depletion Region

When p-type and n-type silicon are joined, diffusion of majority carriers creates a space-charge region (depletion region) depleted of mobile carriers. The built-in electric field (directed n → p) opposes further diffusion. In equilibrium: no net current flows, and the Fermi level is flat throughout.

6.2 The Built-In Potential

The built-in potential (contact potential) is the electrostatic potential difference between the n-side and the p-side in equilibrium:

\[ V_{bi} = V_T \ln\!\left(\frac{N_d N_a}{n_i^2}\right). \]

Derivation. On the n-side, \(E_{Fn} = E_i + k_BT\ln(N_d/n_i)\). On the p-side, \(E_{Fp} = E_i - k_BT\ln(N_a/n_i)\). Since \(E_{Fn} = E_{Fp}\) in equilibrium and the band alignment difference appears as an electrostatic potential step:

\[ eV_{bi} = k_BT\ln(N_d/n_i) + k_BT\ln(N_a/n_i) = k_BT\ln(N_d N_a/n_i^2). \qquad \square \]

For silicon with \(N_a = N_d = 10^{16}\) cm\(^{-3}\): \(V_{bi} \approx 0.717\) V. For \(N_a = 10^{18}\), \(N_d = 10^{15}\): \(V_{bi} = V_T\ln(10^{33}/2.25\times10^{20}) \approx 0.776\) V.

6.3 The Depletion Approximation and Depletion Width

Under the depletion approximation, Poisson’s equation in the depletion region gives an electric field that increases linearly from the depletion edge of each side to a maximum at the metallurgical junction:

\[ \mathcal{E}(x) = -\frac{eN_d}{\varepsilon_s}(x_n - x) \quad \text{for } 0 \leq x \leq x_n, \]\[ \mathcal{E}(x) = +\frac{eN_a}{\varepsilon_s}(x + x_p) \quad \text{for } -x_p \leq x \leq 0. \]

Continuity of \(\mathcal{E}\) at \(x = 0\) gives charge neutrality: \(N_d x_n = N_a x_p\). Integrating \(\mathcal{E}\) across the depletion region gives the total potential drop \(V_{bi} - V_A\):

\[ W = x_n + x_p = \sqrt{\frac{2\varepsilon_s(V_{bi} - V_A)}{e}\left(\frac{1}{N_a} + \frac{1}{N_d}\right)}, \]\[ x_n = \frac{N_a}{N_a + N_d}W, \qquad x_p = \frac{N_d}{N_a + N_d}W. \]

The maximum electric field at \(x = 0\) is:

\[ |\mathcal{E}_{max}| = \frac{eN_d x_n}{\varepsilon_s} = \frac{2(V_{bi} - V_A)}{W}. \]

For a p\(^+\)n junction (\(N_a \gg N_d\)), essentially all the depletion extends into the lightly doped n-side: \(x_n \approx W\), \(x_p \approx 0\), and \(W \approx \sqrt{2\varepsilon_s(V_{bi}-V_A)/(eN_d)}\).

6.4 Minority Carrier Injection and the Ideal Diode Equation

Under forward bias, the boundary conditions at the depletion region edges follow from the quasi-equilibrium assumption (quasi-Fermi level split equals \(eV_A\)):

\[ p_n(x_n) = p_{n0}\exp\!\left(\frac{V_A}{V_T}\right), \qquad n_p(-x_p) = n_{p0}\exp\!\left(\frac{V_A}{V_T}\right). \]

Solving the minority carrier diffusion equation with the decay condition far from the junction:

\[ \delta p_n(x) = p_{n0}\left[\exp\!\left(\frac{V_A}{V_T}\right) - 1\right]e^{-(x-x_n)/L_p}, \qquad x \geq x_n, \]\[ \delta n_p(x) = n_{p0}\left[\exp\!\left(\frac{V_A}{V_T}\right) - 1\right]e^{(x+x_p)/L_n}, \qquad x \leq -x_p. \]

Under forward bias (\(V_A \gg V_T\)): \(J \approx J_s \exp(V_A/V_T)\) — exponential current growth. Under reverse bias (\(V_A \ll -V_T\)): \(J \approx -J_s\) — small temperature-sensitive leakage. The ideal diode model neglects recombination/generation within the depletion region itself; including this (Sah–Noyce–Shockley) adds a component \(\propto \exp(V_A/2V_T)\) that dominates at small forward bias and gives an ideality factor \(n\) between 1 and 2.

6.5 Junction Capacitance

Depletion (junction) capacitance. The capacitance per unit area arises from the variation of depletion charge with voltage:

\[ C_j = \left|\frac{dQ_{dep}}{dV_A}\right| = \frac{\varepsilon_s}{W} = \sqrt{\frac{e\varepsilon_s N_a N_d}{2(N_a+N_d)(V_{bi}-V_A)}}. \]

Plotting \(1/C_j^2\) vs. \(V_A\) gives a straight line: slope \(\propto 1/N_d\) (for a p\(^+\)n junction) and \(x\)-intercept at \(V_{bi}\). This is the basis of C–V profiling for doping characterisation in silicon wafer qualification.

Diffusion (storage) capacitance. Under forward bias, minority carriers stored in the quasi-neutral regions constitute a charge that changes with applied voltage:

\[ C_{diff} \approx \frac{\tau_p I_p + \tau_n I_n}{V_T} \approx \frac{\tau_p I}{V_T} \quad \text{(p\(^+\)n junction)}. \]

The diffusion capacitance is proportional to forward current and dominates under forward bias, making it the relevant capacitance for switching-speed calculations in diode circuits. The total charge-storage time constant \(\tau_s = C_{diff}/g_d = \tau_p\) (minority carrier lifetime) governs the turn-off transient of forward-biased diodes — this is why Schottky diodes (no minority carrier storage) are much faster than p–n junction diodes.

6.6 Reverse Breakdown

At large reverse bias, two mechanisms can produce runaway current.

Zener breakdown occurs in heavily doped junctions (\(N_a, N_d > 10^{17}\) cm\(^{-3}\)) under moderate reverse bias. The thin depletion region (< 10 nm) allows direct band-to-band quantum-mechanical tunnelling — electrons tunnel from the filled valence band of the p-side to the empty conduction band of the n-side. The tunnelling current is exponentially sensitive to barrier thickness and height: \(J_{tunnel} \propto \exp(-4\sqrt{2m^*E_g^3}/(3e\hbar|\mathcal{E}|))\). The temperature coefficient of Zener breakdown voltage is negative.

Avalanche breakdown dominates in more lightly doped junctions. Carriers accelerated across the depletion region gain enough kinetic energy (\(\sim 1.5 E_g\)) to impact-ionise lattice atoms, creating electron–hole pairs. The ionisation rate per unit length is \(\alpha(|\mathcal{E}|)\), which increases strongly with field. Breakdown occurs when multiplication becomes self-sustaining:

\[ \int_0^W \alpha_n(x)\, dx = 1. \]

The avalanche breakdown voltage increases with decreasing doping (wider depletion region at breakdown) and has a positive temperature coefficient (higher temperature means more phonon scattering, less effective impact ionisation, higher breakdown voltage). Breakdown voltages range from a few volts (heavily doped) to hundreds of volts (lightly doped), making avalanche diodes useful as voltage references and transient suppressors.

6.7 Transient Response and Minority Carrier Storage

A forward-biased diode stores minority carriers in the quasi-neutral regions. When the diode is switched from forward to reverse bias, this stored charge must be removed before the diode can withstand reverse voltage. The reverse-recovery transient has two phases:

Phase 1 (storage phase): The excess minority carrier charge is driven out by the reverse current, which initially equals \(I_R = (V_{supply} - 0)/R\) (limited by the external circuit). During this phase, the junction is still slightly forward biased (the stored charge maintains a forward voltage drop). The storage time \(t_s\) satisfies:

\[ t_s \approx \tau_p \ln\!\left(1 + \frac{I_F}{I_R}\right) \qquad \text{(approximate, for long diode)}, \]

where \(I_F\) is the prior forward current and \(I_R\) is the reverse current magnitude.

Phase 2 (recovery phase): Once the excess minority charge near the junction is depleted, the depletion region re-establishes and the reverse current decays toward \(-I_s\). The total reverse recovery time \(t_{rr} = t_s + t_{rec}\) limits the switching frequency of rectifier diodes. Schottky diodes, having no minority carrier storage, have \(t_{rr} \sim\) picoseconds — orders of magnitude faster than p–n junction diodes.

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Chapter 7: Metal–Semiconductor Junctions

7.1 The Schottky Barrier

When a metal contacts an n-type semiconductor, charge transfer aligns the Fermi levels. In the ideal Schottky–Mott model, the barrier height is:

\[ \phi_B = \phi_m - \chi, \]

where \(\phi_m\) is the metal work function and \(\chi\) is the electron affinity of the semiconductor (\(\chi_{Si} = 4.05\) eV). When \(\phi_m > \phi_s\), electrons deplete from the semiconductor surface, forming a rectifying Schottky contact.

The depletion width and capacitance of a Schottky diode follow the same formulas as for a one-sided p\(^+\)n junction:

\[ W = \sqrt{\frac{2\varepsilon_s(V_{bi} - V_A)}{eN_d}}, \qquad C_j = \frac{\varepsilon_s}{W}. \]

7.2 Thermionic Emission and Schottky I–V

Current transport across a Schottky barrier is dominated by thermionic emission of majority carriers over the barrier, rather than minority carrier injection. The Richardson-Dushman equation gives:

\[ J = A^{**}T^2\exp\!\left(-\frac{\phi_B}{V_T}\right)\left[\exp\!\left(\frac{V_A}{V_T}\right) - 1\right]. \]

The effective Richardson constant for silicon is \(A^{**} \approx 110\) A cm\(^{-2}\) K\(^{-2}\) for electrons and \(32\) A cm\(^{-2}\) K\(^{-2}\) for holes. Because \(\phi_B < E_g/e\), the saturation current density of a Schottky diode is orders of magnitude larger than for a p–n junction (\(J_s \propto \exp(-\phi_B/V_T)\) vs. \(J_s \propto n_i^2 \propto \exp(-E_g/V_T)\)). This gives Schottky diodes a lower forward voltage drop (0.2–0.4 V vs. 0.6–0.7 V for silicon p–n), useful in low-voltage rectifier applications and as clamp diodes in digital logic.

7.3 Ohmic Contacts

An ohmic contact carries current in both directions with negligible resistance. Practical ohmic contacts to n-type silicon are made by:

1. Creating a very heavily doped \(n^+\) surface layer (\(N_d > 10^{19}\) cm\(^{-3}\)).
2. Depositing a metal (Al, Ti/TiN, Co or Ni followed by silicidation).

The high doping makes the depletion width \(W \propto N_d^{-1/2}\) thin enough (< 3 nm) for electrons to tunnel through the Schottky barrier, giving low contact resistance \(\rho_c\). The specific contact resistance scales as \(\rho_c \propto \exp(C\sqrt{\phi_B/N_d})\), where \(C\) is a material constant. In modern CMOS, contact resistivity \(\rho_c < 10^{-8}\) \(\Omega\)·cm\(^2\) is required to avoid contact resistance dominating the transistor on-resistance at sub-10-nm nodes.

7.4 Metal–Semiconductor Contacts in Practice: Silicides

In modern CMOS technology, the gate, source, and drain electrodes are made by reacting a thin metal film (cobalt, nickel, titanium) with the underlying silicon to form a metal silicide. Silicidation serves multiple purposes:

• It creates a well-defined, reproducible metal–semiconductor interface with low contact resistance.
• Silicides have high electrical conductivity (\(\rho \approx 10\)–\(20\) μΩ·cm for CoSi\(_2\), NiSi) and serve as low-resistance shunts over the polysilicon gate and source/drain regions.
• The silicidation process is self-aligned (salicide): metal is deposited uniformly, reacts only where silicon is exposed, and the unreacted metal over SiO\(_2\) is selectively etched away. This gives ohmic contacts to both gate and source/drain with no additional lithography step.

The contact resistivity of a silicide–silicon contact depends on the Schottky barrier height and the silicon doping:

\[ \rho_c \propto \exp\!\left(\frac{2\phi_B\sqrt{\varepsilon_s m^*}}{h\sqrt{N_d}}\right). \]

This exponential dependence on \(\sqrt{\phi_B/N_d}\) means that a factor-of-4 increase in doping halves the exponent and dramatically reduces \(\rho_c\). At \(N_d = 10^{20}\) cm\(^{-3}\), \(\rho_c \approx 10^{-8}\) to \(10^{-7}\) Ω·cm\(^2\), acceptable for current CMOS nodes. Below 5-nm nodes, contact resistance to source/drain becomes the dominant parasitic resistance, motivating research into metallic 2D contacts, rare-earth silicides, and semi-metal (bismuth, bismuth–antimony) contacts.

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Chapter 8: The MOS Capacitor

8.1 MOS Structure and the Three Regimes

The MOS capacitor is a parallel plate structure: metal gate / SiO\(_2\) insulator / silicon substrate. The oxide thickness \(t_{ox}\) ranges from 100 nm (1980s CMOS) to below 1.5 nm (modern high-performance CMOS, which uses high-\(\kappa\) dielectrics such as HfO\(_2\) to maintain physical thickness while increasing the equivalent oxide thickness EOT).

For a p-type substrate, three regimes exist:

Accumulation (\(V_G < V_{FB}\)): Negative gate voltage attracts holes. The MOS capacitor presents capacitance \(C_{ox} = \varepsilon_{ox}/t_{ox}\) per unit area.

Depletion (\(V_{FB} < V_G < V_T\)): Positive gate voltage repels holes, creating a depletion layer. Total capacitance:

\[ C = \frac{C_{ox}C_d}{C_{ox} + C_d}, \qquad C_d = \frac{\varepsilon_s}{x_d}. \]

Inversion (\(V_G > V_T\)): At the interface, the band bending is sufficient to create an electron inversion layer. At high frequency (\(f \gg 1/\tau_{gen}\)), the inversion charge cannot respond and capacitance remains at \(C_{ox}C_{d,max}/(C_{ox}+C_{d,max})\). At low frequency, the inversion charge can follow the AC signal and \(C\) returns to \(C_{ox}\). The high-frequency C–V curve is the workhorse for oxide and interface characterisation in semiconductor manufacturing.

8.2 Threshold Voltage Analysis

Strong inversion is defined by surface potential \(\phi_s = 2\phi_F\), where \(\phi_F = V_T\ln(N_a/n_i)\). At this condition, the maximum depletion width is:

\[ x_{d,max} = \sqrt{\frac{4\varepsilon_s\phi_F}{eN_a}}, \]

and the maximum depletion charge per unit area is \(Q_{d,max} = -eN_a x_{d,max}\). The threshold voltage is:

\[ V_T = V_{FB} + 2\phi_F - \frac{Q_{d,max}}{C_{ox}} = V_{FB} + 2\phi_F + \frac{\sqrt{4e\varepsilon_s N_a\phi_F}}{C_{ox}}. \]

8.3 Quantum Effects in Thin Oxides and Inversion Layers

In modern MOSFETs with \(t_{ox} < 3\) nm, two quantum mechanical effects become significant:

Gate oxide tunnelling. When the oxide is thin enough, electrons can tunnel directly from the silicon channel to the gate metal (direct tunnelling current density \(J \propto \exp(-2\kappa t_{ox})\), where \(\kappa = \sqrt{2m_{ox}^*\phi_B}/\hbar\)). For SiO\(_2\) below \(\approx 2\) nm, gate leakage current densities exceed \(10^2\) A/cm\(^2\) at 1 V — unacceptably large for low-power applications. This drove the industry to replace SiO\(_2\) with high-\(\kappa\) dielectrics (HfO\(_2\), \(\varepsilon_r \approx 25\); physical thickness 3–5 nm but equivalent oxide thickness \(\approx 0.5\) nm), which provide the same capacitance with thicker oxide and orders-of-magnitude less tunnelling current.

Quantum confinement in the inversion layer. The inversion layer in a MOSFET is confined to a thin triangular potential well at the Si–SiO\(_2\) interface. The confinement splits the allowed energies into discrete sub-bands. The lowest occupied sub-band energy is above \(E_c\), effectively increasing the threshold voltage and reducing the inversion charge for a given gate voltage compared with the classical model. The quantum correction to threshold voltage is approximately:

\[ \Delta V_T^{QM} \approx \frac{\gamma_{QM}}{C_{ox}} \left(\frac{\mathcal{E}_{surf}}{10^6 \text{ V/cm}}\right)^{2/3}, \]

where \(\gamma_{QM} \approx 0.2\) Å·V for silicon and \(\mathcal{E}_{surf}\) is the surface electric field. At typical surface fields (\(\approx 10^6\) V/cm), this correction is 30–50 mV — comparable to the thermal voltage — and must be included in accurate device models.

8.4 The Body Effect

When the source–body junction is reverse biased (\(V_{SB} > 0\) for NMOS), threshold voltage increases:

\[ V_T(V_{SB}) = V_{T0} + \gamma\!\left(\sqrt{2\phi_F + V_{SB}} - \sqrt{2\phi_F}\right), \]

where the body effect coefficient is \(\gamma = \sqrt{2e\varepsilon_s N_a}/C_{ox}\). The body effect is a three-terminal parameter that appears in all SPICE MOSFET models. In digital circuits, it causes threshold voltage variations in stacked transistors (the lower transistors see source-body reverse bias), limiting stacking depth in logic gates.

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Chapter 9: The MOSFET

9.1 Device Structure and Basic Operation

The n-channel MOSFET (NMOS) has: \(n^+\) source and drain regions in a p-type substrate; a thin gate oxide; and a metal (or doped polysilicon, or metal) gate electrode. The threshold voltage \(V_T\) is the gate voltage at which an inversion layer (channel) forms between source and drain. For \(V_{GS} > V_T\), electrons flow from source to drain when \(V_{DS} > 0\).

9.2 I–V Characteristics by the Gradual Channel Approximation

At position \(x\) along the channel (source at \(x = 0\), drain at \(x = L\)), the local channel potential is \(V(x)\) and the inversion charge density per unit area is:

\[ Q_n(x) = -C_{ox}[V_{GS} - V_T - V(x)]. \]

Current continuity (\(I_D =\) const) and the drift current \(I_D = -W\mu_n Q_n(x) dV/dx\) give, after integration from source to drain:

The transconductance in saturation:

\[ g_m = \frac{\partial I_{D,sat}}{\partial V_{GS}}\bigg|_{V_{DS} = \text{const}} = \mu_n C_{ox}\frac{W}{L}(V_{GS}-V_T) = \sqrt{2\mu_n C_{ox}\frac{W}{L}I_{D,sat}}. \]

The output conductance in saturation:

\[ g_{ds} = \frac{\partial I_{D,sat}}{\partial V_{DS}}\bigg|_{V_{GS} = \text{const}} = \lambda I_{D,sat} \]

where \(\lambda\) (channel-length modulation coefficient) accounts for the shortening of the effective channel length as \(V_{DS}\) exceeds \(V_{DS,sat}\).

9.3 Subthreshold Slope and the 60 mV/decade Limit

Below threshold, the channel is in weak inversion and current flows by diffusion (not drift). The subthreshold drain current is:

\[ I_D \propto \exp\!\left(\frac{V_{GS}}{nV_T}\right), \qquad n = 1 + \frac{C_d}{C_{ox}} \geq 1. \]

The subthreshold slope (the gate voltage needed to change \(I_D\) by one decade) is:

\[ S = 2.303\, nV_T \approx 60\, n \text{ mV/decade at 300 K}. \]

An ideal transistor has \(n = 1\), \(S = 60\) mV/decade. Real silicon MOSFETs have \(S \approx 65\)–90 mV/decade. The 60 mV/decade limit is a fundamental thermodynamic consequence of Boltzmann statistics — it is the reason why scaling MOSFET supply voltage \(V_{DD}\) to near \(V_T\) (for low power) inevitably causes exponential leakage. Transistor concepts that exploit quantum-mechanical tunnelling or steep bandstructure effects (tunnel FETs, negative-capacitance FETs) aim to circumvent this limit.

9.4 MOSFET Small-Signal Model

For small-signal AC analysis of a MOSFET biased in saturation, the circuit model includes:

• Transconductance current source: \(i_d = g_m v_{gs}\), where \(g_m = \mu_n C_{ox}(W/L)(V_{GS}-V_T)\).
• Output resistance: \(r_o = 1/(\lambda I_D) = V_A/I_D\) (channel-length modulation).
• Gate-drain overlap capacitance: \(C_{gd}\) (the Miller capacitance, dominant in amplifier bandwidth limitation).
• Gate-source capacitance: \(C_{gs} = \tfrac{2}{3}C_{ox}WL + C_{gs,overlap}\) (in saturation).
• Body effect transconductance: \(g_{mb} = g_m\gamma/(2\sqrt{2\phi_F + V_{SB}})\).

The intrinsic unity-gain frequency of the MOSFET is:

\[ f_T = \frac{g_m}{2\pi(C_{gs} + C_{gd})} \approx \frac{3\mu_n(V_{GS}-V_T)}{4\pi L^2} \]

(using \(C_{gs} \approx \tfrac{2}{3}C_{ox}WL\) and \(C_{gd} \approx 0\)). This shows that \(f_T \propto 1/L^2\) — a compelling argument for reducing the gate length to improve speed. In modern finFET nodes (L \(\approx\) 5–15 nm), \(f_T > 300\) GHz, comparable to III–V HEMTs. However, at such short lengths, quantum effects (source-to-drain tunnelling), gate oxide leakage, and variability from discrete dopant fluctuations become the dominant engineering challenges.

9.5 CMOS Inverter: Static and Dynamic Operation

The CMOS inverter — one PMOS and one NMOS transistor connected drain-to-drain with complementary inputs — illustrates the key power and speed trade-offs of digital logic.

Static characteristics. When \(V_{in} = 0\) V (logic low), NMOS is off and PMOS is on: output is \(V_{DD}\) (logic high), dissipating essentially no static power (only the off-state leakage \(\approx I_{off} V_{DD}\)). When \(V_{in} = V_{DD}\) (logic high), PMOS is off and NMOS is on: output is 0 V, again negligible static power. The voltage transfer characteristic (VTC) shows a steep transition from high to low in a narrow input range near \(V_{DD}/2\); the slope of the VTC there is \(-g_{mn}r_{on}/(1 + g_{mn}r_{on})\), which for matched transistors approaches \(-g_{mn}(r_{on}/2)\) — the open-loop gain of the inverter at the switching point. Noise margins \(NM_H\) and \(NM_L\) are defined as the maximum input noise that the output can tolerate without crossing the logic threshold.

Dynamic (switching) power. Each logic transition charges or discharges the load capacitance \(C_L\). The energy drawn from the supply in charging \(C_L\) to \(V_{DD}\) is \(C_L V_{DD}^2\), half of which is stored in \(C_L\) and half dissipated in the PMOS. On discharge, the energy stored in \(C_L\) is dissipated in the NMOS. The dynamic power consumption at switching frequency \(f\) with activity factor \(\alpha\) (fraction of cycles with a logic transition) is:

\[ P_{dyn} = \alpha C_L V_{DD}^2 f. \]

This quadratic dependence on \(V_{DD}\) is the primary reason CMOS supply voltages have scaled from 5 V (1980s) to 0.7–1.0 V (modern low-power circuits). Reducing \(V_{DD}\) by 5× reduces dynamic power by 25×. The trade-off is degraded noise margin, exponentially increased subthreshold leakage (\(P_{leak} = I_{off}V_{DD}\)) as \(V_T\) must be scaled proportionally, and slower switching speed (\(t_{pd} \propto C_LV_{DD}/I_{D,sat} \propto V_{DD}/(V_{DD}-V_T)^2\)).

9.6 Short-Channel Effects

As MOSFET channel length \(L\) is reduced below \(\sim 1\) μm, several phenomena degrade ideal behaviour:

Drain-induced barrier lowering (DIBL): The drain depletion region penetrates the channel, reducing the source-side potential barrier and shifting \(V_T\) downward by an amount proportional to \(V_{DS}\). DIBL coefficient \(\eta = -\Delta V_T/\Delta V_{DS}\) is typically 20–100 mV/V for modern transistors.

Velocity saturation: In short channels, carriers reach \(v_{sat}\) before pinch-off. The saturation current becomes \(I_{D,sat} \approx \mu_n C_{ox}(W/L)(V_{GS}-V_T)v_{sat}/(\mu_n+v_{sat}/((V_{GS}-V_T)/L))\), which for very short channels approaches the linear form \(I_{D,sat} \approx C_{ox}Wv_{sat}(V_{GS}-V_T)\) rather than the square-law.

Hot carrier injection: High-energy carriers near the drain impact-ionise, generating electron–hole pairs. Some energetic electrons are injected into the gate oxide, causing threshold voltage drift and oxide degradation — a key reliability concern.

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Chapter 10: Bipolar Junction Transistors

10.1 BJT Physics and the Three-Region Model

The npn BJT has three regions: emitter (n\(^+\)), base (p, thin), collector (n). In forward-active mode: EB junction forward biased, CB junction reverse biased. Electrons are injected from emitter into base; they diffuse across the thin base; they are swept into the collector by the reverse-biased CB junction electric field.

The base must be thin (\(W_B \ll L_n\)) to minimise recombination and maximise current gain. In a short base, the minority carrier profile is approximately linear:

\[ n_p(x) \approx n_{p0}\exp\!\left(\frac{V_{BE}}{V_T}\right)\left(1 - \frac{x}{W_B}\right) + n_{p0}\exp\!\left(\frac{V_{BC}}{V_T}\right)\frac{x}{W_B}. \]

For forward-active mode (\(V_{BC} \ll -V_T\), so the second term \(\approx 0\)):

\[ n_p(x) \approx n_{p0}\exp\!\left(\frac{V_{BE}}{V_T}\right)\left(1 - \frac{x}{W_B}\right). \]

10.2 Collector, Base, and Emitter Currents

The collector current is the diffusion current of minority electrons evaluated at the CB edge (\(x = W_B\)):

\[ I_C = AeD_n\frac{n_{p0}}{W_B}\exp\!\left(\frac{V_{BE}}{V_T}\right) = I_S\exp\!\left(\frac{V_{BE}}{V_T}\right), \]

where the saturation current \(I_S = AeD_n n_i^2/(N_{a,B}W_B)\). Note: \(I_C\) is determined by \(V_{BE}\) only (independent of \(V_{CE}\) in the ideal model) — this is the key property that makes BJTs useful as transconductors.

The base current arises from: (1) back-injection of holes from base into emitter (dominant for a short emitter); (2) recombination in the base; (3) generation–recombination in the CB depletion region. For a long emitter:

\[ I_B = \frac{AeD_p n_i^2}{L_p N_{d,E}}\exp\!\left(\frac{V_{BE}}{V_T}\right). \]

The common-emitter gain:

\[ \beta = \frac{I_C}{I_B} = \frac{D_n N_{d,E} L_p}{D_p N_{a,B} W_B}. \]

10.3 The Early Effect

In practice, \(I_C\) increases slightly with \(V_{CE}\) in the active region, because increasing \(V_{CE}\) widens the CB depletion region, reducing the effective base width \(W_B\). The slope of the \(I_C\)–\(V_{CE}\) characteristic extrapolated back to zero current crosses the voltage axis at \(-V_A\) (the Early voltage, \(V_A \approx 50\)–200 V for silicon BJTs). Including the Early effect:

\[ I_C = I_S\exp\!\left(\frac{V_{BE}}{V_T}\right)\!\left(1 + \frac{V_{CE}}{V_A}\right). \]

The output resistance in the active region is \(r_o = V_A/I_C\), which sets the open-loop gain of a common-emitter amplifier: \(A_v = -g_m r_o = -g_m V_A/I_C = -V_A/V_T\), a fundamental amplifier gain limit.

10.4 The Ebers–Moll Model

The Ebers–Moll model gives a complete two-diode description valid in all four operating regions:

\[ I_C = I_S\left[\exp\!\left(\frac{V_{BE}}{V_T}\right) - 1\right] - \frac{I_S}{\alpha_R}\left[\exp\!\left(\frac{V_{BC}}{V_T}\right) - 1\right], \]\[ I_E = -\frac{I_S}{\alpha_F}\left[\exp\!\left(\frac{V_{BE}}{V_T}\right) - 1\right] + I_S\left[\exp\!\left(\frac{V_{BC}}{V_T}\right) - 1\right], \]

where \(\alpha_F = \beta_F/(\beta_F+1)\) and \(\alpha_R = \beta_R/(\beta_R+1)\) are the forward and reverse common-base gains. In saturation, both junctions are forward biased and the transistor is fully on; the saturation voltage \(V_{CE,sat}\) is:

\[ V_{CE,sat} = V_T\ln\!\left(\frac{1 + I_C/(\beta_R I_B)}{1 - I_C/(\beta_F I_B)}\right) \approx V_T\ln\!\left(\frac{\beta_F}{\beta_R}\right) \cdot \frac{I_B}{I_C} \quad \text{(for deep saturation)}. \]

10.5 BJT Biasing and the DC Load Line

In a common-emitter amplifier, a DC bias sets the operating point. With a base resistor \(R_B\) and collector resistor \(R_C\) (supply \(V_{CC}\)), the load line is:

\[ V_{CE} = V_{CC} - I_C R_C. \]

The Q-point (quiescent operating point) is the intersection of the load line with the transistor characteristic at the chosen \(I_C = \beta I_B = \beta(V_{CC} - V_{BE})/R_B\). Good bias design uses voltage-divider biasing (two resistors \(R_1, R_2\) between \(V_{CC}\) and ground, Thevenin-combined into \(V_{th} = V_{CC}R_2/(R_1+R_2)\) and \(R_{th} = R_1\|R_2\)) and an emitter resistor \(R_E\) to stabilise the Q-point against \(\beta\) variation. The stability factor is \(S = dI_C/dI_{CBO} \approx (1+\beta)/(1 + \beta R_E/(R_{th}+R_E))\), which approaches 1 (ideal stability) when \(\beta R_E \gg R_{th}\). Practically, \(R_E\) is bypassed at signal frequencies by a capacitor \(C_E\) to avoid reducing the AC voltage gain.

The small-signal voltage gain of the common-emitter amplifier is:

\[ A_v = -g_m(R_C\|r_o\|R_L) \approx -\frac{I_C}{V_T}R_C \qquad (r_o \gg R_C, R_L \gg R_C). \]

Substituting \(I_C = V_{CC}/(2R_C)\) (midpoint bias for maximum swing): \(A_v \approx -V_{CC}/(2V_T) \approx -V_{CC}/52\) mV — for \(V_{CC} = 5\) V, \(|A_v| \approx 96\). This sets the order-of-magnitude for BJT voltage gain, dwarfing the MOSFET gain \(g_m R_D\) which is limited by weak inversion considerations.

10.6 High-Frequency Figures of Merit

The unity-gain bandwidth is:

\[ f_T = \frac{g_m}{2\pi(C_{je} + C_{jc})} \approx \frac{1}{2\pi\left(\frac{W_B^2}{2D_n} + \frac{x_{dep,C}}{2v_{sat}} + \frac{C_{je}+C_{jc}}{g_m}\right)}. \]

The base transit time \(\tau_B = W_B^2/(2D_n)\) dominates in conventional BJTs. Modern SiGe HBTs use a graded Ge profile in the base, which creates a built-in electric field that accelerates electrons, reducing the effective transit time to \(\tau_B = W_B^2/(2D_n) \cdot 2\eta/(e^\eta - 1)\) where \(\eta = \Delta E_g/(k_BT)\) is the normalised band gap gradient. With \(\eta \sim 4\) (typical SiGe grading), the transit time is reduced by roughly \(2\eta/e^\eta \cdot e^\eta = 2\eta \approx 8\times\) compared with a uniform base, enabling \(f_T > 500\) GHz.

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Chapter 11: Optical Devices

11.1 Optical Absorption and Photogeneration

When light of photon energy \(h\nu\) enters a semiconductor with \(h\nu \geq E_g\), band-to-band absorption generates electron–hole pairs. The intensity decays as:

\[ I(x) = I_0(1-R)\,e^{-\alpha x}, \]

where \(R\) is the surface reflectivity and \(\alpha\) is the absorption coefficient. The optical generation rate is:

\[ G_{op}(x) = \alpha \Phi_0(1-R)\,e^{-\alpha x}, \]

where \(\Phi_0\) (cm\(^{-2}\)s\(^{-1}\)) is the incident photon flux. For silicon at 600 nm (red): \(\alpha \approx 10^4\) cm\(^{-1}\), so \(1/\alpha = 1\) μm (absorbed near the surface). At 900 nm (near-infrared, close to band edge): \(\alpha \approx 10^2\) cm\(^{-1}\), so \(1/\alpha = 100\) μm (absorbed in the bulk).

11.2 Solar Cells

An illuminated p–n junction diode produces photocurrent \(I_L\) (directed from n to p inside the device — opposite to the forward-bias current direction). The total current is:

\[ I = I_S\left[\exp\!\left(\frac{V_A}{V_T}\right) - 1\right] - I_L. \]

Key figures of merit:

Short-circuit current \(I_{SC} = I_L\): the current delivered when terminals are shorted (\(V_A = 0\)).

Open-circuit voltage:

\[ V_{OC} = V_T\ln\!\left(\frac{I_L}{I_S} + 1\right) \approx V_T\ln\!\left(\frac{I_L}{I_S}\right). \]

Since \(I_S \propto n_i^2 \propto e^{-E_g/k_BT}\) and \(I_L \propto G_{op}\), increasing \(E_g\) increases \(V_{OC}\) but decreases \(I_L\) (because the semiconductor is transparent to sub-gap photons). This trade-off gives an optimal \(E_g \approx 1.3\) eV for single-junction cells illuminated by the solar spectrum (AM1.5).

Fill factor: \(FF = P_{max}/(V_{OC} I_{SC})\), typically 0.75–0.85.

Efficiency: \(\eta = FF \cdot V_{OC} I_{SC}/P_{in}\).

The Shockley–Queisser limit sets \(\eta_{max} \approx 33\%\) for a single-junction cell — losses arise from thermalisation of photons with \(h\nu > E_g + k_BT\) and transparency for \(h\nu < E_g\). Multi-junction cells (e.g., triple-junction GaInP/GaAs/Ge) circumvent the thermalisation limit by assigning each photon to a junction matched to its energy, achieving \(\eta > 45\%\) under concentrated sunlight.

11.3 Photodetectors and Photodiodes

A reverse-biased p–n junction operated as a photodetector converts optical power to electrical current. When light generates electron–hole pairs in or near the depletion region, the built-in electric field sweeps them apart before they can recombine, producing a photocurrent. The device is normally operated under reverse bias to widen the depletion region and improve collection efficiency and speed.

The photocurrent is:

\[ I_{ph} = \frac{e\eta_{ext}P_{opt}}{h\nu}, \]

where \(P_{opt}\) is the incident optical power, \(h\nu\) is the photon energy, and \(\eta_{ext}\) is the external quantum efficiency (fraction of incident photons that produce a collected electron–hole pair). The responsivity is \(\mathcal{R} = I_{ph}/P_{opt} = e\eta_{ext}/(h\nu)\) (A/W). For silicon at 800 nm: \(h\nu = 1.55\) eV, so the maximum responsivity (for \(\eta_{ext} = 1\)) is \(\mathcal{R}_{max} = e/(h\nu) = 0.65\) A/W.

The speed of a p–i–n photodiode (which uses an intrinsic region between p and n for efficient absorption over a wide depletion width) is limited by:

• Transit time across the depletion region: \(\tau_{tr} \approx W/(2v_{sat})\). For \(W = 10\) μm and \(v_{sat} = 10^7\) cm/s: \(\tau_{tr} = 50\) ps.
• RC time constant: \(\tau_{RC} = R_L C_j\), where \(C_j = \varepsilon_s A/W\). A smaller W gives faster transit but larger capacitance — the bandwidth is maximised at an intermediate W.

The signal-to-noise ratio of a photodetector is determined by shot noise (Poisson fluctuations in the photon stream and in the dark current): \(\overline{i_n^2} = 2e(I_{ph} + I_{dark})\Delta f\). For high-sensitivity receivers, avalanche photodiodes (APDs) exploit controlled avalanche gain (internal multiplication factor \(M \gg 1\)) to amplify the photocurrent above the amplifier noise floor, at the cost of added noise from the stochastic multiplication process (excess noise factor \(F(M) = kM + (2-1/M)(1-k) \geq 1\) where \(k = \alpha_p/\alpha_n\)).

11.4 Light-Emitting Diodes

11.4.1 Basic Operation and Efficiency

In a forward-biased p–n junction of a direct-gap semiconductor, injected minority carriers recombine radiatively with majority carriers, emitting photons with \(h\nu \approx E_g\). The internal quantum efficiency is:

\[ \eta_{int} = \frac{\tau_{tot}}{\tau_{rad}} = \frac{1}{1 + \tau_{rad}/\tau_{nr}}, \]

where \(\tau_{tot}^{-1} = \tau_{rad}^{-1} + \tau_{nr}^{-1}\). For GaAs at room temperature, \(\tau_{rad} \approx 1\) ns and \(\tau_{nr} \approx 100\) ns (very good material), giving \(\eta_{int} \approx 99\%\). For silicon, \(\tau_{rad} \approx 10\) ms (indirect gap) while \(\tau_{nr} \approx 10\) μs, giving \(\eta_{int} \approx 0.1\%\) — hopelessly inefficient as an LED.

The external quantum efficiency also accounts for photon extraction. The critical angle for total internal reflection in GaAs (\(n \approx 3.5\)) is \(\theta_c = \sin^{-1}(1/3.5) \approx 17°\), meaning only a cone of solid angle \(\pi\theta_c^2/4\pi \approx 2\%\) can escape from a flat facet. Chip shaping (inverted pyramid, dome), surface roughening, and photonic crystals improve extraction, enabling the best commercial white LEDs to exceed \(\eta_{ext} = 80\%\).

11.4.2 LED Spectral Properties and White Light

The spectral emission of an LED is not a delta function at \(E_g\) but a broadened peak. The spontaneous emission spectrum has a full width at half maximum of approximately \(1.8k_BT \approx 45\) meV at 300 K. For a GaN LED emitting at 450 nm (blue, \(h\nu = 2.75\) eV), this corresponds to a linewidth of \(\approx 20\) nm FWHM. The eye perceives colour primarily by the peak wavelength of the emission.

White light from a single-die LED is most commonly achieved by phosphor down-conversion: a blue InGaN LED excites a Ce:YAG (cerium-doped yttrium aluminium garnet) phosphor that emits a broad yellow band; the mixture of scattered blue light and yellow emission appears white. This approach gives colour rendering indices CRI \(\approx 75\)–90 and wall-plug efficiencies exceeding 200 lm/W in the best laboratory devices, making modern LEDs 10× more efficient than incandescent bulbs and 2–3× more efficient than compact fluorescent lamps.

A key challenge in III-nitride LEDs is efficiency droop: the internal quantum efficiency decreases above a peak injection current density of \(\approx 10\)–50 A/cm\(^2\). The dominant droop mechanism is Auger recombination (\(U_{Auger} = C_n n^3\)) at the high carrier densities generated in narrow quantum wells under high current injection, compounded by polarisation-induced carrier overflow out of the active region. Operating LEDs at lower current density (larger chip area) or in pulsed mode partially mitigates droop at the cost of increased die cost or reduced average power.

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Chapter 12: Semiconductor Device Fabrication — Selected Topics

12.1 Thermal Oxidation of Silicon

The thermal oxide (SiO\(_2\)) formed by exposing silicon to O\(_2\) or H\(_2\)O at 850–1100°C is the foundation of silicon CMOS technology: it serves as the gate dielectric, the field isolation oxide, the diffusion mask, and the passivation layer. The oxidation reaction consumes silicon:

\[ \text{Si} + \text{O}_2 \rightarrow \text{SiO}_2 \qquad \text{(dry oxidation)}, \]\[ \text{Si} + 2\text{H}_2\text{O} \rightarrow \text{SiO}_2 + 2\text{H}_2 \qquad \text{(wet oxidation)}. \]

The oxide grows at the Si–SiO\(_2\) interface: the oxidising species (O\(_2\) or H\(_2\)O) must diffuse through the already-grown oxide. The Deal–Grove model describes oxide thickness \(x_{ox}(t)\) through the implicit relation:

\[ x_{ox}^2 + A x_{ox} = B(t + \tau), \]

where \(B\) (cm\(^2\)/s) is the parabolic rate constant (diffusion-limited, dominant for thick oxides), \(B/A\) (cm/s) is the linear rate constant (interface-reaction-limited, dominant for thin oxides), and \(\tau\) accounts for the initial oxide thickness. For dry O\(_2\) at 1000°C: \(B/A \approx 0.03\) nm/min (initial linear growth) and \(B \approx 0.003\) nm\(^2\)/min (eventually parabolic). Wet oxidation is \(\approx 10\times\) faster because H\(_2\)O has a much higher diffusivity and solubility in SiO\(_2\) than O\(_2\).

A critical fact is that growing a 100 nm oxide consumes 44 nm of silicon (the ratio is the molar volume SiO\(_2\)/Si \(\approx 2.27\)). This must be accounted for in device geometry planning.

12.2 Ion Implantation and Doping Profiles

Ion implantation is the primary method for introducing controlled dopant concentrations into silicon wafers in modern IC fabrication. Dopant ions (B\(^+\), P\(^+\), As\(^+\), etc.) are accelerated to energies of 10–10,000 keV and directed into the wafer surface. The stopping of ions in silicon is governed by nuclear and electronic stopping, and the resulting concentration profile is approximately Gaussian:

\[ N(x) = N_p\exp\!\left(-\frac{(x - R_p)^2}{2\Delta R_p^2}\right), \]

where \(R_p\) is the projected range (peak depth) and \(\Delta R_p\) is the straggle (standard deviation). The peak concentration is \(N_p = Q_{imp}/(\sqrt{2\pi}\,\Delta R_p)\), where \(Q_{imp}\) (ions/cm\(^2\)) is the implant dose. For 100 keV phosphorus in silicon: \(R_p \approx 133\) nm, \(\Delta R_p \approx 51\) nm.

Ion implantation damages the silicon lattice by displacing atoms from their crystalline sites (Frenkel defects). Post-implant annealing at 950–1100°C for seconds to minutes (rapid thermal annealing, RTA) restores crystallinity and electrically activates the dopants (places them on substitutional sites). The dopant profile broadens during annealing by diffusion:

\[ N(x,t) = \frac{Q_{imp}}{2\sqrt{\pi D_t t}}\exp\!\left(-\frac{(x-R_p)^2}{4D_t t}\right), \]

where \(D_t\) is the diffusivity of the dopant at the anneal temperature. Transient enhanced diffusion (TED), caused by the supersaturation of silicon self-interstitials introduced by the implant damage, can temporarily increase dopant diffusivity by 100–10,000× during the early stages of annealing — a crucial effect that limits the achievable junction depth in advanced CMOS.

12.3 CMOS Process Flow (Simplified)

A simplified n-well CMOS process illustrates how the physical concepts from this course translate into fabrication steps:

1. Substrate preparation: p-type (100) silicon wafer, typically 1–10 Ω·cm (\(N_a \approx 10^{15}\) cm\(^{-3}\)).
2. n-well formation: Ion implantation of phosphorus (\(E \approx 500\) keV, \(Q \approx 2\times10^{12}\) cm\(^{-2}\)), followed by drive-in anneal to form a \(1\)–3 μm deep n-well for PMOS.
3. Shallow trench isolation (STI): Etching trenches between device regions, filling with CVD SiO\(_2\), and planarising by CMP. STI replaces the older LOCOS (local oxidation) process for devices below \(\approx 0.25\) μm.
4. Gate stack formation: Thermal oxide (or high-\(\kappa\)/metal gate for modern nodes) + polysilicon or metal gate deposition + gate lithography and etch.
5. Source/drain extension (SDE) implants: Shallow, lightly-doped implants self-aligned to the gate edge, forming the LDD (lightly doped drain) structure to reduce hot-carrier effects.
6. Spacer formation: Sidewall spacers of SiO\(_2\) or Si\(_3\)N\(_4\) are deposited and etched back, setting the offset for the deep source/drain implants.
7. Deep source/drain implants: High-dose As (NMOS) and BF\(_2\) (PMOS) implants self-aligned to the spacer edge.
8. Silicidation (salicide): Ni or Co deposition, reaction with exposed Si to form NiSi or CoSi\(_2\), removal of unreacted metal.
9. Interlayer dielectric and metallisation: CVD SiO\(_2\) or low-\(\kappa\) dielectric planarised by CMP, tungsten plug contacts, Cu dual-damascene interconnects (for advanced nodes).

Each step involves tradeoffs among thermal budget (total thermal energy the dopant profiles can absorb before diffusing excessively), dimensional control, and material compatibility — all governed by the semiconductor physics principles developed in this course.

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Chapter 13: Reference Equations and Material Parameters

12.1 Silicon Material Parameters at 300 K

Parameter	Symbol	Value
Band gap	\(E_g\)	1.12 eV
Intrinsic carrier concentration	\(n_i\)	\(1.5 \times 10^{10}\) cm\(^{-3}\)
Effective density of states, CB	\(N_c\)	\(2.8 \times 10^{19}\) cm\(^{-3}\)
Effective density of states, VB	\(N_v\)	\(1.04 \times 10^{19}\) cm\(^{-3}\)
Electron effective mass (DOS)	\(m^*_{n,dos}\)	\(1.08\, m_0\)
Hole effective mass (DOS)	\(m^*_{p,dos}\)	\(0.56\, m_0\)
Electron mobility	\(\mu_n\)	1350 cm\(^2\)/V·s
Hole mobility	\(\mu_p\)	480 cm\(^2\)/V·s
Electron diffusivity	\(D_n\)	34.9 cm\(^2\)/s
Hole diffusivity	\(D_p\)	12.4 cm\(^2\)/s
Dielectric constant	\(\varepsilon_r\)	11.7
SiO\(_2\) dielectric constant	\(\varepsilon_{ox,r}\)	3.9
Lattice constant	\(a\)	5.431 Å
Thermal voltage (300 K)	\(V_T = k_BT/e\)	25.85 mV
Saturation velocity	\(v_{sat}\)	\(10^7\) cm/s

12.2 GaAs Parameters at 300 K (comparison)

Parameter	GaAs	Si
Band gap \(E_g\)	1.42 eV	1.12 eV
Band structure	Direct	Indirect
\(n_i\)	\(\approx 2\times10^6\) cm\(^{-3}\)	\(1.5\times10^{10}\) cm\(^{-3}\)
\(\mu_n\)	8500 cm\(^2\)/V·s	1350 cm\(^2\)/V·s
\(\mu_p\)	400 cm\(^2\)/V·s	480 cm\(^2\)/V·s
\(\varepsilon_r\)	12.9	11.7

12.3 Compact Equation Reference

Mass-action law (equilibrium):

\[ n_0 p_0 = n_i^2 = N_c N_v \exp\!\left(-\frac{E_g}{k_BT}\right). \]

Carrier concentrations via quasi-Fermi levels:

\[ n = n_i\exp\!\left(\frac{E_{Fn} - E_i}{k_BT}\right), \qquad p = n_i\exp\!\left(\frac{E_i - E_{Fp}}{k_BT}\right). \]

Total current densities:

\[ J_n = e\mu_n n\mathcal{E} + eD_n\frac{dn}{dx} = \mu_n n\frac{dE_{Fn}}{dx}, \]\[ J_p = e\mu_p p\mathcal{E} - eD_p\frac{dp}{dx} = \mu_p p\frac{dE_{Fp}}{dx}. \]

Ideal diode equation:

\[ I = I_S\left[\exp\!\left(\frac{V_A}{V_T}\right) - 1\right], \qquad I_S = Aen_i^2\left(\frac{D_p}{L_p N_d} + \frac{D_n}{L_n N_a}\right). \]

MOSFET saturation current:

\[ I_{D,sat} = \frac{\mu_n C_{ox}}{2}\frac{W}{L}(V_{GS} - V_T)^2(1 + \lambda V_{DS}). \]

BJT transconductance and collector current:

\[ I_C = I_S e^{V_{BE}/V_T}, \qquad g_m = \frac{I_C}{V_T}, \qquad r_o = \frac{V_A}{I_C}. \]

Minority carrier diffusion length:

\[ L = \sqrt{D\tau}. \]

Einstein relation:

\[ D = \frac{k_BT}{e}\mu = V_T\mu. \]

Built-in voltage:

\[ V_{bi} = V_T\ln\!\left(\frac{N_a N_d}{n_i^2}\right). \]

Depletion width (abrupt junction, reverse bias \(-V_R\)):

\[ W = \sqrt{\frac{2\varepsilon_s(V_{bi}+V_R)}{e}\!\left(\frac{1}{N_a}+\frac{1}{N_d}\right)}. \]

Threshold voltage (NMOS on p-type):

\[ V_T = V_{FB} + 2\phi_F + \frac{\sqrt{4e\varepsilon_s N_a \phi_F}}{C_{ox}}, \qquad \phi_F = V_T\ln\!\left(\frac{N_a}{n_i}\right). \]