Sources and References

Primary textbooks — N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications, and Design, 3rd ed., John Wiley & Sons, 2003; D. W. Hart, Power Electronics, McGraw-Hill, 2011. Supplementary texts — R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics, 3rd ed., Springer, 2020; M. H. Rashid, Power Electronics Handbook, 4th ed., Butterworth-Heinemann, 2017. Online resources — MIT OpenCourseWare 6.334 Power Electronics; Colorado Power Electronics Center (CPEC) lecture notes (Erickson).

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Chapter 1: Introduction and Power Semiconductor Devices

1.1 What Is Power Electronics?

Power electronics is the discipline concerned with converting electrical energy from one form to another using semiconductor switching devices. Unlike linear regulators that dissipate excess energy as heat, power electronic converters switch semiconductor devices between their on-state and off-state, achieving high efficiency — often exceeding 90–98% in modern designs.

The four fundamental conversion categories are:

• AC–DC (Rectification): mains power to a regulated DC bus (e.g., power supplies, motor drives front-ends)
• DC–DC (Chopping): stepping a DC voltage up, down, or inverting it (e.g., battery management systems, point-of-load regulators)
• DC–AC (Inversion): DC bus to a controlled AC output (e.g., photovoltaic grid-tie inverters, variable-speed motor drives)
• AC–AC (Cycloconversion or Matrix conversion): direct AC frequency or voltage control

The central challenge in power electronics is achieving high efficiency while meeting load requirements. Every switch transition dissipates energy — minimizing these losses requires careful device selection, gate-drive design, and increasingly, soft-switching techniques.

1.2 Power Semiconductor Devices

1.2.1 The Power Diode

The power diode is a two-terminal, uncontrolled switch. In forward bias the diode conducts with a small on-state voltage drop \(V_F\) typically 0.7–1.5 V. In reverse bias it blocks with a small leakage current.

Reverse recovery is the critical switching limitation. When a conducting diode is abruptly reverse-biased, stored minority carriers must be swept out before the device can block. This produces a reverse-recovery current \(I_{RR}\) and a charge \(Q_{RR}\). The reverse recovery time \(t_{rr}\) has two phases:

\[ t_{rr} = t_a + t_b \]

where \(t_a\) is the interval during which current falls from \(I_F\) through zero and then reaches \(-I_{RR}\), and \(t_b\) is the interval during which the current recovers from \(-I_{RR}\) back to zero.

The reverse recovery charge is:

\[ Q_{RR} = \frac{1}{2} I_{RR} \, t_{rr} \]

Power diodes are classified as general-purpose (slow recovery, line-frequency applications), fast-recovery (reduced \(Q_{RR}\), for switch-mode supplies), and Schottky (near-zero recovery charge, low \(V_F \approx 0.3\text{–}0.5\,\text{V}\), limited to low voltage).

1.2.2 Bipolar Junction Transistor (BJT)

Although largely superseded by MOSFETs and IGBTs, the BJT illustrates fundamental concepts. In power applications the BJT is operated in saturation (on) or cutoff (off). The base-drive current required:

\[ I_B \geq \frac{I_C}{\beta_{forced}} \]

where \(\beta_{forced}\) is chosen conservatively below the current-gain \(h_{FE}\). BJT turn-off is limited by minority carrier storage in the base region, leading to a storage delay time \(t_s\) that restricts maximum switching frequency.

1.2.3 Power MOSFET

The power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a majority-carrier device, making it free of minority-carrier storage delays and therefore very fast. Key parameters:

• On-resistance \(R_{DS(on)}\): the dominant conduction loss parameter. Scales approximately as \(V_{BR}^{2.5}\), making MOSFETs optimal for low-voltage (<200 V) applications.
• Gate charge \(Q_g\): determines gate-drive energy per switching cycle.
• Body diode: an intrinsic antiparallel diode formed by the MOSFET structure, useful in bridge circuits but with moderate reverse recovery.

The MOSFET switching waveforms during turn-on are dominated by charging the gate-drain (Miller) capacitance \(C_{gd}\). During the Miller plateau, \(V_{GS}\) remains approximately constant while \(V_{DS}\) falls.

Switching losses per cycle (approximate):

\[ E_{sw} \approx \frac{1}{2} V_{DS} I_D (t_r + t_f) \]

where \(t_r\) is the rise time and \(t_f\) is the fall time of the drain current.

1.2.4 Insulated Gate Bipolar Transistor (IGBT)

The IGBT combines MOSFET gate control with the lower on-state voltage of a BJT. It is the device of choice for medium-to-high voltage (600 V–6.5 kV) applications such as motor drives and inverters.

Static characteristics: The on-state collector-emitter voltage is:

\[ V_{CE(sat)} \approx V_{junction} + I_C R_{mod} \]

typically 1.5–3.5 V, substantially lower than an equivalent MOSFET at high voltages.

Switching losses — turn-on: When the IGBT turns on into an inductive load, the current rises while voltage remains high (the diode must commutate first). The turn-on energy is approximately:

\[ E_{on} = \frac{1}{2} V_{CE} \cdot I_C \cdot t_{ri} + \frac{1}{2} V_{CE} \cdot I_C \cdot t_{fv} \]

where \(t_{ri}\) is the current rise time and \(t_{fv}\) is the voltage fall time. In practice:

\[ E_{on} \approx \frac{1}{2} V_{bus} I_C t_{on} \]

Switching losses — turn-off: The MOSFET channel turns off quickly but minority carriers in the drift region produce a current tail of duration \(t_{tail}\):

\[ E_{off} = \frac{1}{2} V_{bus} \left( I_C t_{fi} + \frac{I_{tail} \cdot t_{tail}}{2} \right) \]

A simplified engineering estimate often used is:

\[ E_{off} \approx \frac{1}{2} V_{bus} I_C t_{off} \]

The total switching loss at frequency \(f_s\) is:

\[ P_{sw} = (E_{on} + E_{off}) \cdot f_s \]

1.2.5 Thyristor (SCR)

The Silicon Controlled Rectifier (SCR) is a four-layer (PNPN) device. Once triggered into conduction by a gate pulse, it latches on and can only be turned off by reducing the anode current below the holding current (natural or forced commutation). SCRs are used in high-power controlled rectifiers and cycloconverters where their superior surge current capability and low on-state drop are exploited.

Key parameters: gate trigger current \(I_{GT}\), holding current \(I_H\), turn-off time \(t_q\) (typically 10–200 µs for phase-control SCRs).

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Chapter 2: DC-DC Converters — Fundamentals and CCM Analysis

2.1 General Concepts

DC-DC converters transfer power from a DC source to a DC load by periodically connecting and disconnecting the source via a switch. Two energy storage elements — an inductor and a capacitor — filter the switching action. The switch duty cycle \(D\) (fraction of the switching period during which the switch is on) controls the output voltage.

Steady-state assumption: In steady state, every circuit variable is periodic with switching period \(T_s = 1/f_s\). The two key steady-state conditions are:

1. Volt-second balance on the inductor: The average voltage across an inductor in steady state is zero.
2. Amp-second (charge) balance on the capacitor: The average current through a capacitor in steady state is zero.

Continuous Conduction Mode (CCM): The inductor current never reaches zero. This is the normal operating mode for most converters under full load.

Discontinuous Conduction Mode (DCM): The inductor current reaches zero during each switching cycle. This occurs at light loads or with small inductance values.

2.2 Buck (Step-Down) Converter

2.2.1 Circuit Description

The buck converter produces an output voltage \(V_o < V_{in}\). The topology consists of a controlled switch \(S\), a freewheeling diode \(D\), an inductor \(L\), and a filter capacitor \(C\).

• Switch ON, \(0 < t < DT_s\): Diode is reverse-biased. The inductor is connected between \(V_{in}\) and \(V_o\), so \(v_L = V_{in} - V_o > 0\). The inductor current rises linearly.
• Switch OFF, \(DT_s < t < T_s\): The inductor forces the diode into conduction. Now \(v_L = -V_o < 0\). The inductor current falls linearly.

2.2.2 Voltage Conversion Ratio in CCM

Applying volt-second balance:

\[ (V_{in} - V_o) D T_s = V_o (1-D) T_s \]

Solving:

\[ \boxed{M(D) = \frac{V_o}{V_{in}} = D} \]

The output voltage is simply the duty cycle times the input voltage — independent of load in CCM (assuming ideal devices).

2.2.3 Inductor Current Ripple

During the on-time, the inductor voltage is \(V_{in} - V_o\) and the current changes linearly:

\[ \Delta i_L = \frac{(V_{in} - V_o) \cdot D T_s}{L} = \frac{V_{in} D (1-D) T_s}{L} \]

where the substitution \(V_{in} - V_o = V_{in}(1-D)\) (using \(V_o = V_{in} D\)) was made. This is the peak-to-peak ripple. The peak inductor current is:

\[ I_{L,peak} = I_o + \frac{\Delta i_L}{2} = \frac{V_o}{R} + \frac{V_{in} D (1-D) T_s}{2L} \]

2.2.4 Output Voltage Ripple

Assuming the ripple current flows entirely through the capacitor (a valid approximation for large \(C\)):

\[ \Delta V_o = \frac{\Delta i_L}{8 f_s C} = \frac{V_{in} D (1-D)}{8 L C f_s^2} \]

Equivalently, using \(\Delta i_L = V_o(1-D)/(Lf_s)\):

\[ \frac{\Delta V_o}{V_o} = \frac{(1-D)}{8 L C f_s^2} \]

If the capacitor has equivalent series resistance \(R_{ESR}\), an additional ripple term \(\Delta V_{ESR} = \Delta i_L \cdot R_{ESR}\) must be added.

2.2.5 CCM/DCM Boundary Condition

At the CCM–DCM boundary, the minimum inductor current just touches zero. The average (equal to \(I_o\)) equals half the peak-to-peak ripple:

\[ I_{o,crit} = \frac{\Delta i_L}{2} = \frac{V_{in} D (1-D) T_s}{2L} = \frac{V_o (1-D)}{2 L f_s} \]

The critical inductance below which DCM begins at a given load \(I_o\):

\[ L_{crit} = \frac{(1-D) R}{2 f_s} \]

where \(R = V_o/I_o\) is the load resistance.

2.2.6 Buck Converter in DCM

In DCM, the inductor current rises from zero during \(D T_s\) and falls back to zero in time \(D_2 T_s\), where \(D_2 < 1-D\). The third interval \(D_3 = 1-D-D_2\) has zero inductor current (diode off, switch off).

Volt-second balance still applies (the on-interval and off-interval must balance):

\[ (V_{in} - V_o) D = V_o D_2 \implies D_2 = \frac{(V_{in} - V_o)D}{V_o} \]

The average inductor current (which equals \(I_o\) at steady state) in DCM:

\[ I_o = \frac{1}{2} \cdot \frac{(V_{in}-V_o) D T_s}{L} \cdot (D+D_2) \]

Defining \(K = 2L/(RT_s)\), the voltage conversion ratio in DCM can be derived by combining the above equations. After algebraic manipulation:

\[ M_{DCM} = \frac{V_o}{V_{in}} = \frac{2}{1 + \sqrt{1 + 4K/D^2}} \]

This shows that in DCM, the conversion ratio depends on load — as load decreases (R increases, K decreases), \(V_o/V_{in}\) rises toward 1.

2.2.7 Inductor and Capacitor Design

Inductor selection: Choose \(L\) to limit ripple current to a desired fraction of full-load current, typically \(\Delta i_L / I_o \leq 0.2\text{–}0.4\):

\[ L = \frac{V_o (1-D)}{\Delta i_L \cdot f_s} \]

Capacitor selection: Choose \(C\) to meet the output ripple voltage specification:

\[ C = \frac{\Delta i_L}{8 f_s \Delta V_o} \]

The capacitor must also handle the RMS ripple current:

\[ I_{C,rms} = \frac{\Delta i_L}{2\sqrt{3}} \]

2.3 Boost (Step-Up) Converter

2.3.1 Circuit Description

The boost converter produces \(V_o > V_{in}\). It consists of an inductor \(L\) in series with the source, a switch \(S\) to ground, a diode \(D\), and a filter capacitor \(C\).

• Switch ON: Inductor stores energy; \(v_L = V_{in}\), current rises. Diode is reverse-biased; capacitor supplies load.
• Switch OFF: Inductor releases energy through diode to capacitor and load; \(v_L = V_{in} - V_o < 0\).

2.3.2 Voltage Conversion Ratio (CCM)

Volt-second balance:

\[ V_{in} \cdot D T_s = (V_o - V_{in})(1-D)T_s \]\[ \boxed{M(D) = \frac{V_o}{V_{in}} = \frac{1}{1-D}} \]

As \(D \to 1\), \(M \to \infty\) theoretically. In practice, parasitic resistances limit the maximum achievable voltage gain.

2.3.3 Inductor Ripple and Design

\[ \Delta i_L = \frac{V_{in} \cdot D}{L f_s} = \frac{V_o (1-D) D}{L f_s} \]

Critical inductance:

\[ L_{crit} = \frac{D(1-D)^2 R}{2 f_s} \]

where \(R = V_o^2/P_o\).

2.3.4 Output Capacitor Ripple (Boost)

The diode only conducts during the off-time \((1-D)T_s\), so the capacitor must supply all the load current during the on-time:

\[ \Delta V_o = \frac{V_o D}{R C f_s} = \frac{I_o D}{C f_s} \]

2.4 Buck-Boost Converter

2.4.1 Operation

The buck-boost can produce an output voltage either higher or lower than the input, but with reversed polarity. Topology: switch \(S\) connects source to inductor; when switch is off, the inductor discharges through diode into the capacitor (which is oriented with opposite polarity to the source).

• Switch ON: \(v_L = V_{in}\), inductor current rises.
• Switch OFF: \(v_L = -V_o\) (with the sign convention that \(V_o > 0\) for the magnitude of the output), inductor current falls.

2.4.2 Voltage Conversion Ratio (CCM)

\[ V_{in} \cdot D = V_o (1-D) \]\[ \boxed{M(D) = \frac{V_o}{V_{in}} = \frac{D}{1-D}} \]

At \(D = 0.5\), \(\lvert V_o \rvert = V_{in}\). For \(D < 0.5\) the converter steps down; for \(D > 0.5\) it steps up.

2.4.3 Inductor and Capacitor Design

Peak-to-peak inductor ripple:

\[ \Delta i_L = \frac{V_{in} D}{L f_s} \]

Output capacitor ripple voltage:

\[ \Delta V_o = \frac{V_o D}{R C f_s} \]

2.5 Cuk and SEPIC Converters

2.5.1 Cuk Converter

The Cuk converter (named after Slobodan Cuk) achieves non-inverting buck-boost operation using a capacitor for energy transfer. It has two inductors and two capacitors. Key advantages: both input and output currents are continuous (reduced EMI). The voltage conversion ratio in CCM is identical to the buck-boost:

\[ M(D) = \frac{V_o}{V_{in}} = \frac{D}{1-D} \]

but \(V_o\) has the same polarity as \(V_{in}\) in the standard Cuk implementation (non-inverting with appropriate winding arrangement).

2.5.2 SEPIC Converter

The Single-Ended Primary Inductance Converter (SEPIC) also achieves non-inverting buck-boost. It uses two inductors (which may share a core), one coupling capacitor, and one output capacitor. The voltage gain in CCM:

\[ M(D) = \frac{D}{1-D} \]

SEPIC is popular in battery-powered applications where the input voltage varies above and below the required output.

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Chapter 3: Control of DC-DC Converters

3.1 Average-Switch Model

To design a feedback controller, we need a small-signal linearized model of the converter. The average-switch model (also called the averaged PWM switch model) replaces the switch-diode pair with a linear two-port characterized by averaged quantities.

3.1.1 State-Space Averaging for the Buck Converter

Define state variables: inductor current \(i_L\) and capacitor voltage \(v_C \approx V_o\). During the two subintervals:

Subinterval 1 (switch on, \(0 < t < DT_s\)):

\[ \frac{d i_L}{dt} = \frac{V_{in} - v_C}{L}, \quad \frac{d v_C}{dt} = \frac{i_L - v_C/R}{C} \]

Subinterval 2 (switch off, \(DT_s < t < T_s\)):

\[ \frac{d i_L}{dt} = \frac{-v_C}{L}, \quad \frac{d v_C}{dt} = \frac{i_L - v_C/R}{C} \]

Forming the averaged state equations (weighting by \(D\) and \(1-D\)):

\[ \frac{d \langle i_L \rangle}{dt} = \frac{D V_{in} - \langle v_C \rangle}{L}, \quad \frac{d \langle v_C \rangle}{dt} = \frac{\langle i_L \rangle - \langle v_C \rangle / R}{C} \]

3.1.2 Small-Signal Perturbation

Perturb around the operating point: \(d = D + \hat{d}\), \(v_{in} = V_{in} + \hat{v}_{in}\), \(i_L = I_L + \hat{i}_L\), \(v_C = V_C + \hat{v}_C\). Substituting and dropping second-order (product of small-signal) terms:

\[ L \frac{d \hat{i}_L}{dt} = D \hat{v}_{in} + V_{in} \hat{d} - \hat{v}_C \]\[ C \frac{d \hat{v}_C}{dt} = \hat{i}_L - \frac{\hat{v}_C}{R} \]

3.1.3 Control-to-Output Transfer Function

Taking Laplace transforms with \(\hat{v}_{in} = 0\) (line rejection analysis) and solving for \(\hat{v}_C(s)/\hat{d}(s)\):

\[ G_{vd}(s) = \frac{\hat{v}_o(s)}{\hat{d}(s)} = \frac{V_{in}}{1 + s\frac{L}{R} + s^2 LC} \]

This is a second-order low-pass transfer function with DC gain \(V_{in}\), natural frequency:

\[ \omega_0 = \frac{1}{\sqrt{LC}} \]

and quality factor:

\[ Q = R\sqrt{\frac{C}{L}} \]

The resonance frequency \(f_0 = \omega_0/(2\pi)\) corresponds to a double pole in the Bode plot (−40 dB/dec rolloff, −180° phase shift) — a challenging feature for feedback loop compensation.

3.2 Voltage-Mode Control

In voltage-mode control (VMC), only the output voltage is sensed. The feedback loop compares \(V_o\) to a reference \(V_{ref}\) and adjusts \(D\) via a PWM comparator.

The open-loop gain \(T(s)\) of the voltage-mode buck converter:

\[ T(s) = G_c(s) \cdot G_{vd}(s) \cdot \frac{1}{V_M} \]

where \(G_c(s)\) is the compensator transfer function and \(V_M\) is the PWM ramp amplitude.

3.2.1 Type II Compensator (PI-Lead)

A type II compensator provides one integrator (for zero steady-state error) plus one zero-pole pair for phase boost:

\[ G_c(s) = \frac{K_c (1 + s/\omega_z)}{s(1 + s/\omega_p)} \]

Design guidelines: place the zero at \(f_z \approx f_0/\sqrt{10}\) to provide phase boost near crossover; place the pole at \(f_p \approx f_{sw}/2\) to attenuate switching-frequency ripple.

3.2.2 Type III Compensator

For converters with high-ESR capacitors (where the ESR zero appears below the crossover frequency), a type III compensator with two zeros and two poles is used, enabling phase margin of 45–60° at higher crossover frequencies.

3.3 Current-Mode Control

Peak current-mode control (PCMC) uses two feedback loops: an inner current loop that terminates the switch on-time when the inductor current reaches a commanded reference \(i_{ref}(t)\), and an outer voltage loop that sets \(i_{ref}\).

Advantages of PCMC:

• Inherent overcurrent limiting
• Elimination of the LC double pole in the outer loop (simplified compensation)
• Improved line rejection

Slope compensation: Without slope compensation, PCMC is unstable for \(D > 0.5\). Adding a stabilizing ramp of slope \(m_c \geq m_2/2\) (where \(m_2 = V_o/L\) is the inductor current downslope) eliminates subharmonic oscillation.

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Chapter 4: AC-DC Converters (Rectifiers)

4.1 Single-Phase Diode Bridge Rectifier

4.1.1 Full-Wave Bridge Topology

The single-phase full-wave diode bridge uses four diodes in an H-bridge arrangement. The output voltage \(v_o(t)\) is a full-wave rectified sinusoid:

\[ v_o(t) = \lvert V_s \sin(\omega t) \rvert = V_m \lvert \sin(\omega t) \rvert \]

where \(V_m = \sqrt{2} V_{rms}\) is the peak source voltage.

Average output voltage (resistive load):

\[ V_{dc} = \frac{2 V_m}{\pi} \approx 0.637 V_m = 0.9 V_{rms} \]

RMS output voltage:

\[ V_{rms,o} = \frac{V_m}{\sqrt{2}} = V_{rms} \]

Form factor:

\[ FF = \frac{V_{rms,o}}{V_{dc}} = \frac{\pi}{2\sqrt{2}} \approx 1.11 \]

Ripple factor:

\[ RF = \sqrt{FF^2 - 1} \approx 0.482 \]

4.1.2 Output Voltage Ripple with Capacitive Load

When a large filter capacitor \(C\) is connected, the diodes only conduct near the peaks of the source voltage. Between peaks, the capacitor discharges into the load at rate \(V_o/RC\). The peak-to-peak ripple is approximately:

\[ \Delta V_o \approx \frac{V_m}{f_{ripple} \cdot R C} = \frac{I_{dc}}{2 f_s C} \]

where \(f_{ripple} = 2f_s\) for a full-wave rectifier (ripple frequency is twice the supply frequency). This leads to:

\[ \Delta V_o \approx \frac{I_{dc}}{2 f_s C} \]

4.1.3 Power Factor and THD

With a capacitive load, the diode bridge draws pulsed current from the source. This non-sinusoidal current contains harmonic components. The power factor:

\[ PF = \frac{P}{S} = \frac{I_{1,rms}}{I_{rms}} \cos\phi_1 \]

where \(I_{1,rms}\) is the fundamental RMS current, \(I_{rms}\) is the total RMS current, and \(\phi_1\) is the displacement angle of the fundamental.

The Total Harmonic Distortion (THD) of the source current is:

\[ THD = \frac{\sqrt{I_{rms}^2 - I_{1,rms}^2}}{I_{1,rms}} = \sqrt{\sum_{n=2}^{\infty} \left(\frac{I_n}{I_1}\right)^2} \]

A single-phase diode bridge with a large capacitor typically has \(THD \approx 60\text{–}130\%\) and \(PF \approx 0.5\text{–}0.7\), which is why power factor correction (PFC) stages are mandated by standards such as IEC 61000-3-2.

4.2 Three-Phase Diode Bridge Rectifier

The three-phase diode bridge (six-pulse bridge) consists of six diodes. The upper group conducts whichever phase has the highest instantaneous voltage; the lower group conducts whichever phase has the lowest.

Average output voltage:

\[ V_{dc} = \frac{3\sqrt{3}}{\pi} V_{m,\phi} = \frac{3\sqrt{6}}{\pi} V_{phase,rms} \approx 1.35 V_{LL,rms} \]

where \(V_{LL,rms}\) is the line-to-line RMS voltage.

Ripple frequency: 6 times supply frequency (six-pulse output). The peak-to-peak ripple is much smaller than the single-phase case, approximately 5% of \(V_{dc}\).

THD of line current: approximately 31% (due to 5th and 7th harmonics being dominant, with the 6k±1 harmonic series present).

4.3 Single-Phase Thyristor (Phase-Controlled) Rectifier

In the phase-controlled rectifier, SCRs replace diodes. The firing angle \(\alpha\) delays the gating pulse relative to the natural commutation point (voltage zero-crossing).

Average output voltage (single-phase fully-controlled bridge, resistive or highly inductive load):

\[ V_o(\alpha) = \frac{2 V_m}{\pi} \cos\alpha \]

The output voltage is controllable from \(+2V_m/\pi\) (at \(\alpha = 0\)) to \(-2V_m/\pi\) (at \(\alpha = \pi\)), enabling four-quadrant DC drive operation when combined with a reversible motor.

4.4 Three-Phase Thyristor Bridge Rectifier

The three-phase fully-controlled bridge (six thyristors in the standard bridge configuration) produces:

\[ \boxed{V_o(\alpha) = \frac{3\sqrt{2}}{\pi} V_{LL} \cos\alpha \approx 1.35 V_{LL} \cos\alpha} \]

where \(V_{LL}\) is the line-to-line RMS voltage. This is often written as \(V_o = 2.34 V_{ph}\cos\alpha\) where \(V_{ph}\) is the phase RMS voltage. Noting \(V_{LL} = \sqrt{3} V_{ph}\):

\[ V_o(\alpha) = \frac{3\sqrt{6}}{\pi} V_{ph} \cos\alpha \approx 2.34 V_{ph} \cos\alpha \]

The SCRs are fired in sequence at \(60°\) intervals, delayed by \(\alpha\) from the natural commutation point. For \(\alpha < 90°\) the bridge operates in rectifier mode (positive average output); for \(90° < \alpha < 180°\) it operates in inverter mode (negative average output), allowing energy regeneration from a DC machine back to the AC supply.

4.4.1 Commutation Overlap

In practical circuits, the AC source has inductance \(L_s\). During commutation between SCRs, the current transfer is not instantaneous — it occurs over an overlap angle \(\mu\). The average output voltage is reduced:

\[ V_o = \frac{3\sqrt{6}}{\pi} V_{ph} \cos\alpha - \frac{3 \omega L_s}{\pi} I_d \]

The voltage drop \(3\omega L_s I_d/\pi\) acts as a commutation reactance voltage drop.

4.5 Power Factor Correction (PFC)

Active PFC inserts a boost converter between the bridge rectifier and the DC bus. The boost converter is controlled to draw sinusoidal input current in phase with the source voltage, achieving \(PF \approx 0.99\) and \(THD < 5\%\). The control uses average current-mode control with a multiplier to shape the current reference according to the rectified source voltage waveform.

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Chapter 5: DC-AC Inverters

5.1 Single-Phase H-Bridge Inverter

5.1.1 Topology

The H-bridge (full-bridge) inverter consists of four switches arranged in two legs. Switches \(S_1, S_4\) form one diagonal; \(S_2, S_3\) form the other. Each switch is typically an IGBT with an antiparallel diode.

5.1.2 Bipolar PWM

In bipolar sinusoidal PWM, switches are driven in complementary pairs (\(S_1/S_2\) and \(S_3/S_4\)). The output voltage alternates between \(+V_{dc}\) and \(-V_{dc}\).

The reference sinusoid \(v_{ref}(t) = M_a \sin(\omega_o t)\) is compared to a triangular carrier of amplitude \(V_{tri}\) at frequency \(f_s\). The modulation index:

\[ M_a = \frac{\hat{V}_{ref}}{V_{tri}} \]

Fundamental output voltage amplitude (bipolar):

\[ \hat{V}_{o,1} = M_a V_{dc}, \quad 0 \leq M_a \leq 1 \]

Harmonic spectrum: Voltage harmonics appear at \(f_s\) and sidebands \(f_s \pm 2f_o\), \(2f_s\), \(2f_s \pm f_o\), \(2f_s \pm 3f_o\), etc. The dominant harmonic in bipolar PWM is at the carrier frequency \(f_s\).

5.1.3 Unipolar PWM

In unipolar PWM, each leg is switched using its own phase-shifted reference. Leg A uses \(+v_{ref}\); Leg B uses \(-v_{ref}\). The output \(v_{AB}\) switches between \(+V_{dc}\), 0, and \(-V_{dc}\).

Advantages of unipolar PWM:

• Output voltage effectively switches at \(2f_s\) (phase-leg voltages switch at \(f_s\), but their difference switches at twice the frequency)
• Lower output current ripple for same \(f_s\)
• Dominant harmonics appear at \(2f_s\) and sidebands — much easier to filter

Fundamental output voltage (unipolar): Same as bipolar — \(\hat{V}_{o,1} = M_a V_{dc}\).

THD comparison: Unipolar PWM typically achieves significantly lower THD than bipolar PWM at the same switching frequency.

5.1.4 Overmodulation

When \(M_a > 1\), the reference waveform exceeds the carrier peak during some portions of the cycle. The fundamental output voltage increases beyond \(M_a V_{dc}\) toward the square-wave limit of \(\frac{4}{\pi} V_{dc}\). This region (\(1 < M_a \leq 3.24\) approximately) trades increased fundamental for increased harmonic content.

5.2 Three-Phase Voltage Source Inverter (VSI)

5.2.1 Topology

The three-phase VSI has three half-bridge legs connected to a common DC bus \(V_{dc}\). Each leg produces a phase output that switches between \(+V_{dc}/2\) and \(-V_{dc}/2\) (with respect to the DC bus midpoint). The six switches are labeled \(S_1\)–\(S_6\).

5.2.2 Sinusoidal PWM for Three-Phase VSI

Each phase reference is a sinusoid phase-shifted by 120°:

\[ v_{ref,a} = M_a \sin(\omega_o t), \quad v_{ref,b} = M_a \sin(\omega_o t - 120°), \quad v_{ref,c} = M_a \sin(\omega_o t + 120°) \]

Each is compared to a common triangular carrier. The output phase voltages and line-to-line voltages:

Fundamental phase voltage amplitude:

\[ \hat{V}_{AN,1} = M_a \frac{V_{dc}}{2}, \quad 0 \leq M_a \leq 1 \]

Fundamental line-to-line voltage amplitude:

\[ \hat{V}_{LL,1} = \sqrt{3} M_a \frac{V_{dc}}{2} \approx 0.866 M_a V_{dc} \]

Maximum fundamental with linear modulation (sinusoidal PWM):

\[ \hat{V}_{LL,max} = 0.866 V_{dc} \]

Third-harmonic injection can extend this: the third harmonic \((M_{a,3}/6) \cdot \hat{V}_{tri}\) added to each reference does not appear in line-to-line voltages but allows \(M_a\) to reach \(2/\sqrt{3} \approx 1.155\) while keeping phase voltages within the rail, giving:

\[ \hat{V}_{LL,max,THI} = V_{dc}/\sqrt{2} \times \sqrt{2} \cdot \ldots = \frac{V_{dc}}{\sqrt{3}} \cdot \sqrt{3} = V_{dc} \]

More precisely with 1/6 third-harmonic injection, the maximum achievable fundamental line-to-line voltage is \(V_{dc}\), matching the square-wave limit.

5.3 Space-Vector PWM (SVPWM)

5.3.1 Voltage Space Vectors

In a three-phase VSI, each switch state is represented by a switching vector \(\mathbf{S} = (S_a, S_b, S_c)\) where \(S_k = 1\) means the upper switch of leg \(k\) is on. There are \(2^3 = 8\) possible switch states, producing 6 active vectors and 2 zero vectors.

The complex space vector for a given switch state:

\[ \mathbf{V} = \frac{2}{3} V_{dc} \left( S_a + S_b e^{j2\pi/3} + S_c e^{j4\pi/3} \right) \]

The six active voltage vectors \(\mathbf{V}_1\) through \(\mathbf{V}_6\) have magnitude \(\frac{2}{3}V_{dc}\) and are separated by 60° in the complex plane. The two zero vectors \(\mathbf{V}_0 = (0,0,0)\) and \(\mathbf{V}_7 = (1,1,1)\) produce zero output.

Voltage vector table:

Vector	\(S_a S_b S_c\)	Angle
\(\mathbf{V}_1\)	100	0°
\(\mathbf{V}_2\)	110	60°
\(\mathbf{V}_3\)	010	120°
\(\mathbf{V}_4\)	011	180°
\(\mathbf{V}_5\)	001	240°
\(\mathbf{V}_6\)	101	300°
\(\mathbf{V}_0\)	000	—
\(\mathbf{V}_7\)	111	—

5.3.2 Sector Identification

The reference vector \(\mathbf{V}_{ref}\) rotates at the fundamental frequency \(\omega_o\). The space vector plane is divided into 6 sectors of 60° each. Sector identification from the angle \(\theta\) of \(\mathbf{V}_{ref}\):

\[ \text{Sector} = \left\lfloor \frac{\theta}{60°} \right\rfloor + 1, \quad \theta \in [0°, 360°) \]

5.3.3 Duty Cycle Calculation (Sector 1 Example)

In Sector 1 (\(0° \leq \theta < 60°\)), the reference is synthesized from adjacent vectors \(\mathbf{V}_1\) (100) and \(\mathbf{V}_2\) (110) plus zero vectors:

\[ \mathbf{V}_{ref} T_s = \mathbf{V}_1 T_1 + \mathbf{V}_2 T_2 + \mathbf{V}_0 (T_0/2) + \mathbf{V}_7 (T_0/2) \]

where \(T_1 + T_2 + T_0 = T_s\). Solving:

\[ T_1 = \sqrt{3} \frac{\lvert \mathbf{V}_{ref} \rvert}{V_{dc}} T_s \sin(60° - \theta) \]\[ T_2 = \sqrt{3} \frac{\lvert \mathbf{V}_{ref} \rvert}{V_{dc}} T_s \sin(\theta) \]\[ T_0 = T_s - T_1 - T_2 \]

Maximum modulation index (SVPWM): The largest circle inscribed in the hexagon of voltage vectors has radius \(V_{dc}/\sqrt{3}\). The maximum fundamental phase voltage is:

\[ \hat{V}_{ph,max} = \frac{V_{dc}}{\sqrt{3}} \]

giving \(\hat{V}_{LL,max} = V_{dc}\), which is 15.5% higher than sinusoidal PWM without third-harmonic injection. This is one reason SVPWM is preferred in industrial drives.

5.3.4 Switching Sequence and Harmonic Performance

The switching sequence in Sector 1 is typically: \(\mathbf{V}_0 \to \mathbf{V}_1 \to \mathbf{V}_2 \to \mathbf{V}_7 \to \mathbf{V}_2 \to \mathbf{V}_1 \to \mathbf{V}_0\). This symmetric sequence minimizes switching transitions per cycle (only one switch changes state at each transition) and produces low harmonic content equivalent to sinusoidal PWM with optimal third-harmonic injection.

5.4 Harmonic Analysis of Inverter Output

The output voltage of a PWM inverter is analyzed using double Fourier series. The harmonic content depends on the modulation scheme, modulation index, and switching frequency ratio \(m_f = f_s/f_o\).

For a three-phase VSI with sinusoidal PWM (odd \(m_f\), multiple of 3), triplen harmonics in the phase voltages do not appear in the line-to-line voltages. The lowest-order line-to-line harmonics are at \(m_f \pm 2\), \(2m_f \pm 1\).

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Chapter 6: Motor Drives and Applications

6.1 DC Motor Speed Control

6.1.1 DC Motor Equivalent Circuit

A separately-excited DC motor is modeled as a back-EMF source \(E_a\) in series with armature resistance \(R_a\) and armature inductance \(L_a\):

\[ V_a = E_a + I_a R_a + L_a \frac{dI_a}{dt} \]

The back-EMF is proportional to speed and field flux:

\[ E_a = K_\phi \omega_m = K_\phi \frac{2\pi N}{60} \]

Electromagnetic torque:

\[ T_e = K_\phi I_a \]

where \(K_\phi = K \Phi\) with \(\Phi\) the field flux and \(K\) the motor constant.

At steady state:

\[ \omega_m = \frac{V_a - I_a R_a}{K_\phi} = \frac{V_a}{K_\phi} - \frac{R_a}{K_\phi^2} T_e \]

This is the speed-torque characteristic — a slightly drooping line with slope \(-R_a/K_\phi^2\).

6.1.2 Speed Control via Armature Voltage (DC-DC Converter)

The most efficient and flexible speed control method uses a DC-DC converter to adjust the armature voltage \(V_a\). A chopper (typically a buck converter for motoring-only, or an H-bridge for four-quadrant operation) feeds the armature.

Operating regions:

• Constant-torque (below base speed): Armature voltage is varied from 0 to rated voltage \(V_{a,rated}\) while maintaining rated field flux. Speed varies proportionally to \(V_a\). Maximum torque equals rated torque.

• Field weakening (above base speed): Once \(V_a = V_{a,rated}\), further speed increase is achieved by reducing field current \(I_f\), which reduces \(\Phi\) and hence \(K_\phi\). Speed increases as \(\omega_m \propto 1/K_\phi\). Since \(V_a = E_a = K_\phi \omega_m\) is maintained constant, and rated armature current is maintained, the output power is constant while torque decreases as \(T_e = K_\phi I_a \propto 1/\omega_m\). This is constant-power (field-weakening) operation.

6.1.3 Four-Quadrant DC Drive

An H-bridge converter driving a DC motor allows operation in all four quadrants of the torque-speed plane:

• Quadrant I: Forward motoring (\(V_a > 0\), \(I_a > 0\), \(T_e > 0\), \(\omega > 0\))
• Quadrant II: Forward regenerative braking (\(V_a > 0\), \(I_a < 0\), \(T_e < 0\), \(\omega > 0\))
• Quadrant III: Reverse motoring
• Quadrant IV: Reverse regenerative braking

The PWM H-bridge (bipolar or unipolar) can smoothly transition between quadrants without mechanical contactors.

6.1.4 Speed Control Loop Design

The motor speed control system typically uses a cascaded control structure:

1. Inner current (torque) loop: Fast PI controller; bandwidth \(\approx f_s/10\text{–}f_s/5\). Limits armature current to protect the motor and converter.
2. Outer speed loop: Slower PI controller; bandwidth \(\approx 1/10\) of current loop bandwidth. Provides the current reference.

The current-loop bandwidth is limited by the armature time constant \(\tau_a = L_a/R_a\) and the switching frequency.

6.1.5 DC Motor Lab: Speed Control via Buck Converter

In the laboratory implementation (Lab 3), a buck converter supplies the DC motor armature. The duty cycle \(D\) is the control input:

\[ V_a = D \cdot V_{dc} \]

At steady state, motor speed:

\[ \omega_m \approx \frac{D V_{dc}}{K_\phi} \]

(neglecting armature resistance drop, which is valid at high speed). The speed is adjusted by varying \(D\) using a PWM controller. The armature inductance helps filter the switching current ripple; if insufficient, a separate series inductor is added.

6.2 AC Induction Motor Drives

6.2.1 Variable-Frequency Drive (VFD) Principle

An induction motor’s synchronous speed:

\[ n_s = \frac{120 f}{P} \]

where \(f\) is the supply frequency and \(P\) is the number of poles. Speed control is achieved by varying \(f\). To maintain constant air-gap flux (and thus constant maximum torque), the voltage-to-frequency ratio must be kept constant:

\[ \frac{V}{f} = \text{constant} \quad \Rightarrow \quad V = V_{rated} \cdot \frac{f}{f_{rated}} \]

This is scalar V/f (Volts/Hertz) control, implemented by a three-phase VSI with SVPWM.

6.2.2 Field-Oriented Control (FOC)

Field-oriented (vector) control decouples the flux-producing and torque-producing components of the stator current by transforming to a rotating reference frame aligned with the rotor flux. In this frame, the d-axis current \(i_{sd}\) controls flux and the q-axis current \(i_{sq}\) controls torque:

\[ T_e = \frac{3}{2} \frac{P}{2} \psi_r i_{sq} / L_m' \]

FOC achieves dynamic performance comparable to separately-excited DC drives. It requires real-time coordinate transformations (Clarke and Park transforms) and either a flux observer or a shaft encoder.

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Chapter 7: Resonant and Soft-Switching Converters

7.1 Switching Losses and the Motivation for Soft Switching

In hard-switched converters, every switch transition involves simultaneous non-zero voltage and current, leading to switching losses \(P_{sw} = (E_{on} + E_{off})f_s\). As \(f_s\) increases to reduce passive component size, switching losses grow linearly. Soft-switching techniques aim to ensure either zero voltage (\(v_{sw} = 0\)) or zero current (\(i_{sw} = 0\)) at the switching instant.

7.2 Zero-Current Switching (ZCS)

In ZCS, the switch turns on and off when its current is zero. This is achieved by adding a resonant inductor in series with the switch. The inductor limits \(di/dt\) at turn-on and naturally brings the current to zero before turn-off.

A ZCS quasi-resonant switch cell replaces the conventional switch. The resonant tank formed by \(L_r\) and \(C_r\) with resonant frequency:

\[ f_r = \frac{1}{2\pi\sqrt{L_r C_r}} \]

determines the timing. The output voltage is controlled by varying the switching frequency \(f_s < f_r\).

7.3 Zero-Voltage Switching (ZVS)

In ZVS, the switch voltage is reduced to zero (or a body-diode voltage) before the switch turns on. This eliminates capacitive turn-on losses \((\frac{1}{2} C_{oss} V_{DS}^2 f_s)\) and avoids the reverse-recovery problem of the diode. ZVS is preferred at high voltage and high frequency (e.g., LLC resonant converter for server power supplies).

7.3.1 LLC Resonant Converter

The LLC converter uses two resonant inductors (\(L_r\) and the magnetizing inductance \(L_m\)) and one resonant capacitor \(C_r\). At the series resonant frequency \(f_{rs} = 1/(2\pi\sqrt{L_r C_r})\), the converter exhibits minimum circulating current and ZVS for the primary switches. The voltage gain:

\[ M(f, Q) = \frac{V_o}{V_{in}/n} = \frac{f_n^2}{\sqrt{(f_n^2 - 1)^2 Q^2 f_n^2 + (f_n^2(1+L_n^{-1}) - 1)^2}} \]

where \(f_n = f_s/f_{rs}\) is the normalized frequency and \(Q\) is the quality factor. Frequency modulation controls the gain.

7.4 Phase-Shifted Full-Bridge (PSFB) Converter

The PSFB converter uses four switches in a full-bridge configuration with fixed 50% duty cycle per switch, but with a phase shift \(\phi\) between the leading and lagging legs. ZVS is achieved for all four switches using the energy stored in the resonant inductance (transformer leakage + external \(L_r\)) and the switch output capacitances. The effective duty cycle controlling power transfer:

\[ D_{eff} = 1 - \frac{\phi}{180°} \]

The PSFB is widely used in telecom and data center power supplies (48 V bus, 1–5 kW range).

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Chapter 8: Simulation of Power Electronic Circuits

8.1 PSIM Simulation Environment

PSIM (Power Simulation) is a dedicated power electronics simulator optimized for switched-mode converter analysis. Unlike general-purpose SPICE simulators, PSIM uses simplified switch models that converge quickly even at high switching frequencies.

Key simulation elements in PSIM:

• Controlled switches: ideal MOSFET, IGBT, diode — switchable between ideal and detailed device models
• Gate/base drive blocks: pulse generators for PWM, comparators for current-mode control
• Probes: voltage probes (across elements), current probes (in series), power meters
• AC sweep: small-signal Bode plot analysis for control loop verification
• DLL interface: C/C++ code blocks for custom control algorithms

8.1.1 Convergence and Timestep

The simulation timestep \(\Delta t\) must satisfy:

\[ \Delta t \leq \frac{T_s}{100\text{–}1000} \]

to accurately resolve switching transients. For a converter at \(f_s = 100\,\text{kHz}\), a timestep of 10–100 ns is typical.

8.1.2 Steady-State Analysis

To measure steady-state ripple and average values, simulation must run for enough cycles for the initial transient to decay. For a converter with time constant \(\tau = RC\), run for at least \(5\tau\). PSIM’s built-in FFT function computes the harmonic spectrum of any periodic waveform.

8.2 Simulation Methodology for DC-DC Converters (Lab 2)

Open-loop verification:

1. Build the converter circuit (buck, boost, or buck-boost) with ideal switches.
2. Apply a fixed duty cycle via pulse generator.
3. Measure \(V_o\), \(\Delta i_L\), \(\Delta V_o\) at steady state and compare to theoretical predictions.
4. Vary duty cycle and plot \(V_o/V_{in}\) vs. \(D\) — confirm the theoretical conversion ratio.

Closed-loop verification:

1. Add compensator (type II or III) and PWM comparator.
2. Perform AC sweep to obtain Bode plots of loop gain.
3. Verify phase margin (target 45–60°) and crossover frequency.
4. Apply load step and observe transient response.

8.3 Inverter Simulation (Lab 4)

For the single-phase H-bridge inverter:

1. Implement bipolar sinusoidal PWM using triangle wave carrier and sinusoidal reference.
2. Measure output voltage \(v_{AB}\) and load current.
3. Run FFT to identify fundamental and harmonic components; compute THD.
4. Repeat for unipolar PWM and compare harmonic content.

For the three-phase VSI:

1. Implement SVPWM using a lookup table or algorithmic block.
2. Measure line-to-line voltage and phase current (with balanced RL load).
3. Compare fundamental voltage amplitude at different modulation indices.
4. Observe that line-to-line voltages do not contain triplen harmonics.

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Chapter 9: Design Examples and Worked Problems

9.1 Buck Converter Complete Design Example

Specifications:

• \(V_{in} = 24\,\text{V}\), \(V_o = 12\,\text{V}\), \(I_o = 5\,\text{A}\)
• \(f_s = 100\,\text{kHz}\), \(\Delta i_L / I_o \leq 20\%\), \(\Delta V_o / V_o \leq 1\%\)

Step 1: Duty cycle.

\[ D = \frac{V_o}{V_{in}} = \frac{12}{24} = 0.5 \]

Step 2: Inductor design.

\[ \Delta i_L = 0.20 \times 5 = 1\,\text{A} \]\[ L = \frac{V_o(1-D)}{\Delta i_L \cdot f_s} = \frac{12 \times 0.5}{1 \times 100 \times 10^3} = 60\,\mu\text{H} \]

Verify using the ripple formula:

\[ \Delta i_L = \frac{V_{in} D(1-D)}{L f_s} = \frac{24 \times 0.5 \times 0.5}{60 \times 10^{-6} \times 10^5} = \frac{6}{6} = 1\,\text{A} \checkmark \]

Step 3: Capacitor design.

\[ \Delta V_o = 0.01 \times 12 = 0.12\,\text{V} \]\[ C = \frac{\Delta i_L}{8 f_s \Delta V_o} = \frac{1}{8 \times 10^5 \times 0.12} = 10.4\,\mu\text{F} \]

Choose \(C = 22\,\mu\text{F}\) (standard value, with adequate voltage rating and low ESR).

Step 4: CCM/DCM boundary check.

\[ I_{o,crit} = \frac{V_o(1-D)}{2Lf_s} = \frac{12 \times 0.5}{2 \times 60 \times 10^{-6} \times 10^5} = \frac{6}{12} = 0.5\,\text{A} \]

Since \(I_o = 5\,\text{A} \gg 0.5\,\text{A}\), the converter operates in CCM.

Step 5: Peak switch current.

\[ I_{sw,peak} = I_o + \frac{\Delta i_L}{2} = 5 + 0.5 = 5.5\,\text{A} \]

Step 6: RMS switch and diode currents.

\[ I_{sw,rms} = I_o \sqrt{D} = 5\sqrt{0.5} = 3.54\,\text{A} \]\[ I_{D,rms} = I_o \sqrt{1-D} = 5\sqrt{0.5} = 3.54\,\text{A} \]

Step 7: Switching losses (MOSFET example).

Assume \(t_{on} = t_{off} = 50\,\text{ns}\):

\[ E_{sw} = \frac{1}{2} V_{in} I_o (t_{on} + t_{off}) = \frac{1}{2} \times 24 \times 5 \times 100 \times 10^{-9} = 6\,\mu\text{J} \]\[ P_{sw} = E_{sw} \times f_s = 6 \times 10^{-6} \times 10^5 = 0.6\,\text{W} \]

Step 8: Conduction losses.

Assuming \(R_{DS(on)} = 25\,\text{m}\Omega\):

\[ P_{cond} = I_{sw,rms}^2 R_{DS(on)} = 3.54^2 \times 0.025 = 0.31\,\text{W} \]

Step 9: Efficiency estimate.

\[ P_{out} = V_o I_o = 12 \times 5 = 60\,\text{W} \]\[ \eta \approx \frac{P_{out}}{P_{out} + P_{sw} + P_{cond} + P_{diode}} \approx \frac{60}{60 + 0.6 + 0.31 + 0.5} \approx 97.5\% \]

9.2 Boost Converter Design Example

Specifications: \(V_{in} = 12\,\text{V}\), \(V_o = 24\,\text{V}\), \(P_o = 60\,\text{W}\), \(f_s = 50\,\text{kHz}\), ripple \(\leq 2\%\).

\[ D = 1 - \frac{V_{in}}{V_o} = 1 - 0.5 = 0.5 \]\[ I_o = \frac{P_o}{V_o} = 2.5\,\text{A}, \quad I_{in} = \frac{P_o}{V_{in}} = 5\,\text{A} \]

Inductor (10% ripple on input current):

\[ L = \frac{V_{in} D}{\Delta i_L f_s} = \frac{12 \times 0.5}{0.5 \times 50 \times 10^3} = 240\,\mu\text{H} \]

Capacitor:

\[ C = \frac{I_o D}{\Delta V_o f_s} = \frac{2.5 \times 0.5}{0.02 \times 24 \times 50000} = 52\,\mu\text{F} \]

9.3 IGBT Switching Loss Calculation Example

Given: Three-phase inverter, \(V_{dc} = 600\,\text{V}\), \(I_C = 30\,\text{A}\), \(f_s = 10\,\text{kHz}\). From IGBT datasheet (at \(V_{CE} = 600\,\text{V}\), \(I_C = 30\,\text{A}\)): \(E_{on} = 3\,\text{mJ}\), \(E_{off} = 2\,\text{mJ}\), \(E_{rr} = 1\,\text{mJ}\) (diode reverse recovery).

Total switching energy per commutation:

\[ E_{total} = E_{on} + E_{off} + E_{rr} = 6\,\text{mJ} \]

Per-switch average switching loss (approximately, for sinusoidal modulation with modulation index \(M_a = 1\)):

\[ P_{sw,IGBT} = \frac{(E_{on} + E_{off}) f_s}{\pi} \cdot \frac{I_{C,peak}}{I_{C,rated}} \]

For a single IGBT at full load:

\[ P_{sw} = (E_{on} + E_{off}) \times f_s = 5 \times 10^{-3} \times 10^4 = 50\,\text{W} \]

For all six IGBTs in the three-phase inverter (each switching once per carrier cycle):

\[ P_{sw,total} \approx 6 \times 50 = 300\,\text{W} \]

plus diode reverse recovery: \(6 \times E_{rr} \times f_s = 6 \times 1 \times 10^{-3} \times 10^4 = 60\,\text{W}\).

This total switching loss (\(\approx 360\,\text{W}\)) for a 18-kW drive represents about 2% switching loss — consistent with high-efficiency industrial inverters.

9.4 Three-Phase Thyristor Bridge: Firing Angle Calculation

Problem: A three-phase fully-controlled bridge rectifier is connected to a 208 V (line-to-line, rms) supply. Determine the firing angle \(\alpha\) required to produce an average output voltage of 200 V with a highly inductive load.

\[ V_o = 1.35 \times V_{LL} \cos\alpha \]\[ 200 = 1.35 \times 208 \times \cos\alpha \]\[ \cos\alpha = \frac{200}{280.8} = 0.712 \]\[ \alpha = \cos^{-1}(0.712) \approx 44.6° \]

RMS value of fundamental phase current (for 6-pulse bridge with ideal current waveform):

The AC line current waveform is a quasi-square wave with flat tops at \(+I_d\) and \(-I_d\) each for 120° and zeros for 60°. The fundamental RMS:

\[ I_{1,rms} = \frac{\sqrt{6}}{\pi} I_d \approx 0.780 \, I_d \]

Total RMS current of the quasi-square wave:

\[ I_{rms} = \sqrt{\frac{2}{3}} I_d \approx 0.816 \, I_d \]

Power factor (at \(\alpha\)):

\[ PF = \frac{I_{1,rms}}{I_{rms}} \cos\alpha = \frac{0.780}{0.816} \times 0.712 \approx 0.680 \]

THD of source current:

\[ THD = \frac{\sqrt{I_{rms}^2 - I_{1,rms}^2}}{I_{1,rms}} = \frac{\sqrt{0.816^2 - 0.780^2}}{0.780} \approx 31\% \]

9.5 Single-Phase H-Bridge: THD and Output Filter Design

Problem: A single-phase H-bridge inverter with \(V_{dc} = 400\,\text{V}\), \(f_o = 60\,\text{Hz}\), \(f_s = 5\,\text{kHz}\), \(M_a = 0.9\), unipolar PWM, drives a resistive load of \(R = 10\,\Omega\). Design an output LC filter to limit current ripple THD at the load to < 5%.

Fundamental output voltage:

\[ \hat{V}_{o,1} = M_a \cdot V_{dc} = 0.9 \times 400 = 360\,\text{V (peak)} \]\[ V_{o,1,rms} = \frac{360}{\sqrt{2}} = 254.6\,\text{V} \]

Dominant harmonic (unipolar, at \(2f_s = 10\,\text{kHz}\)):

The harmonic voltage amplitude at \(2f_s\) is approximately (from Bessel function analysis) \(J_0(M_a \pi/2) \cdot V_{dc} \approx 0.2 V_{dc} = 80\,\text{V}\) peak. For a filter with:

\[ f_{lc} = \frac{1}{2\pi\sqrt{LC}} \]

The attenuation at \(2f_s\) relative to the LC corner:

\[ \text{Att} = \left(\frac{f_{lc}}{2f_s}\right)^2 \]

Setting \(f_{lc} = 1\,\text{kHz}\) (well above \(f_o = 60\,\text{Hz}\), well below \(2f_s = 10\,\text{kHz}\)):

\[ \text{Att} = \left(\frac{1000}{10000}\right)^2 = 0.01 \]

Harmonic voltage at load \(\approx 80 \times 0.01 = 0.8\,\text{V}\) peak. THD of load voltage \(\approx 0.8/360 = 0.22\%\). This is well within specification.

Component values (for \(f_{lc} = 1\,\text{kHz}\) with \(L = 1\,\text{mH}\)):

\[ C = \frac{1}{(2\pi f_{lc})^2 L} = \frac{1}{(2\pi \times 1000)^2 \times 10^{-3}} = 25.3\,\mu\text{F} \]

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Chapter 10: Advanced Topics and Design Considerations

10.1 Thermal Management

10.1.1 Thermal Equivalent Circuit

The junction-to-ambient thermal path is modeled as a series thermal resistance network:

\[ T_j = T_a + P_{loss}(R_{\theta,jc} + R_{\theta,cs} + R_{\theta,sa}) \]

where:

• \(T_j\) — junction temperature (must remain below \(T_{j,max}\), typically 125–175°C for IGBTs)
• \(T_a\) — ambient temperature
• \(R_{\theta,jc}\) — junction-to-case thermal resistance (from datasheet)
• \(R_{\theta,cs}\) — case-to-heatsink thermal resistance (depends on mounting and thermal interface material)
• \(R_{\theta,sa}\) — heatsink-to-ambient thermal resistance (determines heatsink size)

10.1.2 Junction Temperature Under Switching Conditions

Total power dissipated per IGBT:

\[ P_{total} = P_{cond} + P_{sw} = I_{C,rms}^2 \cdot r_{CE} + V_{CE0} \cdot I_{C,avg} + (E_{on} + E_{off}) f_s \]

where \(V_{CE0}\) and \(r_{CE}\) are the threshold voltage and slope resistance from the output characteristics.

10.2 EMI and Filtering

10.2.1 Sources of EMI

Power converters generate both conducted and radiated EMI due to high \(dv/dt\) and \(di/dt\) at switching instants. The switching node of a buck converter transitions at:

\[ \frac{dv}{dt} = \frac{V_{in}}{t_r} \]

For \(V_{in} = 400\,\text{V}\) and \(t_r = 10\,\text{ns}\): \(dv/dt = 40\,\text{V/ns}\). This excites parasitic capacitances and produces high-frequency common-mode and differential-mode currents.

10.2.2 EMI Filter Design

A two-stage LC filter (differential mode) is typically placed at the converter input. The filter must attenuate switching harmonics to meet conducted EMI limits (e.g., CISPR 22 Class B: 46 dBµV from 150 kHz–500 kHz).

Common-mode EMI is addressed with a common-mode choke (coupled inductors with high common-mode impedance) plus Y-capacitors to the safety ground.

10.3 Magnetics Design for Power Electronics

10.3.1 Core Material Selection

The core material for the inductor or transformer determines maximum flux density \(B_{sat}\) and core loss density \(P_v\). At high frequencies:

• Ferrite (e.g., MnZn): Low loss at 20 kHz–1 MHz, \(B_{sat} \approx 0.3\text{–}0.5\,\text{T}\). Most common for switch-mode supplies.
• Powder cores (Kool-Mu, MPP): Distributed gap, suitable for inductors with large DC bias.
• Amorphous/nanocrystalline: Higher \(B_{sat}\) (0.8–1.2 T), low loss at 20–100 kHz, used in high-power inductors.

10.3.2 Inductor Design Procedure

1. Compute inductance \(L\) from ripple specification.
2. Compute peak current \(I_{pk}\): ensures core does not saturate.
3. Select core using the area product method: \(A_c A_w \geq \frac{L I_{pk}^2}{B_{max} J_{max} K_u}\) where \(A_c\) is core cross-section, \(A_w\) is window area, \(J_{max}\) is current density, \(K_u\) is window utilization factor.
4. Calculate number of turns: \(N = L I_{pk} / (B_{max} A_c)\).
5. Determine air gap for required inductance and DC bias handling: \(\ell_g = \mu_0 N^2 A_c / L\).
6. Verify winding resistance and resulting copper loss.

10.3.3 Transformer Design (Flyback, Forward)

Transformer design follows a similar area-product approach but includes both primary \(N_p\) and secondary \(N_s\) turns. The turns ratio \(n = N_p/N_s\) sets the conversion ratio. Isolation requires adequate creepage and clearance distances per safety standards (IEC 60950-1, UL 60950-1).

10.4 Synchronous Rectification

Replacing the freewheeling diode in a buck converter with a synchronous MOSFET (\(S_2\)) reduces conduction loss from \(V_F I_o \approx 0.5\text{–}1\,\text{V} \times I_o\) to \(I_o^2 R_{DS(on)}\). At low output voltages (1.2–3.3 V) and high currents, synchronous rectification is essential for high efficiency.

The synchronous MOSFET must be driven with a gate signal complementary to the main switch, with a small dead-time (50–100 ns) to prevent shoot-through. During dead-time, the body diode conducts (or a Schottky diode in parallel reduces the voltage drop).

10.5 Interleaved Converters

Paralleling \(N\) converter phases with switching instants offset by \(T_s/N\) is called interleaving. The input and output current ripple frequencies multiply by \(N\), while the ripple amplitude decreases dramatically. For \(N\) interleaved buck converters:

\[ \Delta I_{o,interleaved} \leq \frac{\Delta I_{o,single}}{N} \]

(exact cancellation occurs at specific duty cycles). This allows smaller filter components and lower EMI, at the cost of \(N\) independent control channels.

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Chapter 11: Summary of Key Formulas

11.1 Converter Conversion Ratios (Ideal, CCM)

Converter	\(M(D) = V_o/V_{in}\)	CCM condition
Buck	\(D\)	\(L > \frac{(1-D)R}{2f_s}\)
Boost	\(\frac{1}{1-D}\)	\(L > \frac{D(1-D)^2 R}{2f_s}\)
Buck-Boost	\(\frac{D}{1-D}\)	\(L > \frac{(1-D)^2 R}{2f_s}\)
Cuk	\(\frac{D}{1-D}\)	Both inductors in CCM
SEPIC	\(\frac{D}{1-D}\)	Both inductors in CCM

11.2 Buck Converter Key Equations

Inductor ripple:

\[ \Delta i_L = \frac{V_{in} D(1-D)}{L f_s} = \frac{V_o(1-D)}{L f_s} \]

Output voltage ripple:

\[ \Delta V_o = \frac{\Delta i_L}{8 C f_s} = \frac{V_o(1-D)}{8LCf_s^2} \]

Voltage conversion ratio (DCM):

\[ M_{DCM} = \frac{2}{1 + \sqrt{1 + 4K/D^2}}, \quad K = \frac{2L}{RT_s} \]

Small-signal control-to-output transfer function:

\[ G_{vd}(s) = \frac{V_{in}}{1 + \frac{s}{\omega_0 Q} + \frac{s^2}{\omega_0^2}}, \quad \omega_0 = \frac{1}{\sqrt{LC}}, \quad Q = R\sqrt{\frac{C}{L}} \]

11.3 Rectifier Voltages

Rectifier type	Average output voltage
Single-phase half-wave	\(0.318 V_m\)
Single-phase full-wave	\(0.637 V_m = 0.9 V_{rms}\)
Three-phase diode bridge	\(1.35 V_{LL,rms}\)
Three-phase controlled bridge	\(1.35 V_{LL,rms} \cos\alpha\)

11.4 Inverter Fundamentals

Fundamental output — single-phase H-bridge:

\[ \hat{V}_{o,1} = M_a V_{dc} \quad (M_a \leq 1, \text{ bipolar or unipolar PWM}) \]

Fundamental line voltage — three-phase VSI (SPWM):

\[ \hat{V}_{LL,1} = \sqrt{3} \frac{M_a V_{dc}}{2} = \frac{\sqrt{3}}{2} M_a V_{dc} \]

Maximum fundamental line voltage:

\[ \hat{V}_{LL,max} = V_{dc} \quad \text{(SVPWM or SPWM with 3rd harmonic injection)} \]

11.5 SVPWM Duty Cycles (Sector 1)

\[ T_1 = \sqrt{3} \frac{\lvert\mathbf{V}_{ref}\rvert}{V_{dc}} T_s \sin(60° - \theta) \]\[ T_2 = \sqrt{3} \frac{\lvert\mathbf{V}_{ref}\rvert}{V_{dc}} T_s \sin\theta \]\[ T_0 = T_s - T_1 - T_2 \]

11.6 IGBT Losses

Conduction loss:

\[ P_{cond} = V_{CE0} I_{C,avg} + r_{CE} I_{C,rms}^2 \]

Switching loss:

\[ P_{sw} = (E_{on} + E_{off}) f_s \]

Junction temperature:

\[ T_j = T_a + (P_{cond} + P_{sw})(R_{\theta,jc} + R_{\theta,cs} + R_{\theta,sa}) \]

11.7 DC Motor Speed-Torque

Speed-torque characteristic:

\[ \omega_m = \frac{V_a}{K_\phi} - \frac{R_a}{K_\phi^2} T_e \]

Field weakening speed range:

\[ \frac{\omega_{max}}{\omega_{base}} = \frac{K_{\phi,rated}}{K_{\phi,min}} = \frac{\Phi_{rated}}{\Phi_{min}} \]

Armature voltage control (constant flux):

\[ \omega_m \propto V_a = D \cdot V_{dc} \]

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