Sources and References

Primary reference — S. A. Campbell, Fabrication Engineering at the Micro- and Nanoscale, 4th ed., Oxford University Press, 2013. Supplementary texts — S. M. Sze and M-K. Lee, Semiconductor Devices: Physics and Technology, 3rd ed., Wiley, 2012; R. C. Jaeger, Introduction to Microelectronic Fabrication, 2nd ed., Prentice Hall, 2002. Online resources — MIT OpenCourseWare 6.152J Micro/Nano Processing Technology; NIST/SEMATECH e-Handbook of Semiconductor Manufacturing Technology (www.nist.gov).

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Chapter 1: Semiconductor Crystal Growth

1.1 Why Crystal Quality Matters

Semiconductor devices depend on the periodic lattice of a crystal to produce the band structure that gives rise to controlled electrical behaviour. Defects — vacancies, interstitials, dislocations, grain boundaries — introduce mid-gap trap states that scatter carriers and degrade minority-carrier lifetime. For a silicon solar cell or a CMOS transistor, even parts-per-billion concentrations of certain transition-metal impurities can catastrophically reduce device performance. Crystal growth is therefore not merely a materials science problem; it is the first process step of every microelectronic fabrication sequence.

1.2 The Czochralski Process

The dominant commercial method for producing single-crystal silicon is the Czochralski (CZ) technique, which accounts for roughly 95 % of all silicon boule production.

1.2.1 Process Sequence

1. Electronic-grade polysilicon (purity \( > 99.9999999\% \), i.e. 9N) is loaded into a fused silica (SiO\(_2\)) crucible.
2. The charge is melted by radiofrequency or resistive heating at \( T_m = 1412\,^\circ\text{C} \).
3. A small single-crystal seed, oriented along \(\langle 100 \rangle\) or \(\langle 111 \rangle\), is brought into contact with the melt surface.
4. After a short neck region (the Dash neck, used to eliminate dislocations seeded by thermal shock), the crystal is slowly pulled upward while both the crystal and crucible rotate in opposite directions to homogenise melt composition.
5. The pull rate and heater power are adjusted to control diameter. Modern CZ systems grow 300 mm diameter boules to lengths exceeding 2 m.

1.2.2 Dopant Incorporation — the Segregation Coefficient

As the crystal solidifies, impurity atoms partition between solid and liquid phases according to the equilibrium segregation coefficient:

\[ k_0 = \frac{C_s}{C_l} \]

where \(C_s\) is the dopant concentration in the solid and \(C_l\) is the concentration in the adjacent liquid. For boron (p-type dopant in silicon), \(k_0 \approx 0.8\); for phosphorus, \(k_0 \approx 0.35\); for arsenic, \(k_0 \approx 0.3\). Because \(k_0 < 1\) for most dopants, rejected impurities accumulate in the melt as pulling progresses, driving the solid concentration upward toward the tail of the boule. The Scheil equation describes the solid concentration as a function of the fraction solidified \(g\):

\[ C_s(g) = k_0 C_0 (1 - g)^{k_0 - 1} \]

where \(C_0\) is the initial melt concentration. Resistivity therefore varies along a CZ boule, and wafers from near the seed differ from those near the tail.

1.2.3 Oxygen and Carbon in CZ Silicon

The fused silica crucible dissolves into the melt, introducing interstitial oxygen at concentrations of \(10^{17}\)–\(10^{18}\,\text{cm}^{-3}\). This oxygen is mostly electrically inactive but can precipitate during subsequent thermal processing, forming oxide precipitates that act as intrinsic gettering sites for metallic impurities — a beneficial effect exploited deliberately. Carbon is also incorporated from graphite furnace components at lower concentrations (\( \sim 10^{16}\,\text{cm}^{-3} \)).

1.3 Float-Zone Refining

For applications requiring extremely low oxygen (high-resistivity detectors, power devices), the float-zone (FZ) process is preferred. A polysilicon rod is passed through a narrow radiofrequency-heated zone. Impurities with \(k_0 < 1\) are swept toward the tail in successive passes, achieving resistivities > 10 kΩ·cm. The FZ method produces no crucible-derived oxygen, but maximum diameter is limited to about 200 mm due to surface-tension constraints on the molten zone.

1.4 Epitaxial Growth

Epitaxy (from Greek: arranged on top) refers to single-crystal film deposition where the film’s crystallographic orientation is determined by the substrate. It enables:

• Abrupt doping profile control not achievable by bulk growth.
• Heterojunction formation (e.g., SiGe on Si for HBTs, GaAs on AlGaAs for HEMTs).
• Controlled thickness layers for SOI (silicon-on-insulator) wafer fabrication.

1.4.1 Homoepitaxy vs. Heteroepitaxy

In homoepitaxy the film and substrate are the same material (Si on Si). In heteroepitaxy they differ (Ge on Si). Lattice mismatch \(\varepsilon = (a_f - a_s)/a_s\) (where \(a_f\) and \(a_s\) are the film and substrate lattice parameters) determines whether growth is pseudomorphic (strained, coherent) or relaxed (misfit dislocations form above the critical thickness \(h_c\)).

1.4.2 Chemical Vapor Deposition (CVD) Epitaxy

Silicon epitaxy is typically performed by thermal CVD using silane (SiH\(_4\)) or trichlorosilane (SiHCl\(_3\)):

\[ \text{SiH}_4(g) \rightarrow \text{Si}(s) + 2\,\text{H}_2(g) \quad (\sim 650\text{–}1000\,^\circ\text{C}) \]

Growth rate is limited either by the surface reaction rate (at low temperatures, Arrhenius behaviour) or by mass transport of reactants to the surface (at high temperatures, weakly temperature-dependent). In the mass-transport-limited regime, the growth rate is:

\[ R = \frac{h_g C_g}{N_{Si}} \]

where \(h_g\) is the gas-phase mass-transfer coefficient, \(C_g\) is the reactant concentration in the bulk gas, and \(N_{Si}\) is the atomic density of silicon (\(5 \times 10^{22}\,\text{cm}^{-3}\)).

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Chapter 2: Vacuum and Plasma Processes

2.1 Fundamentals of Vacuum Technology

Many thin-film deposition and etching processes occur at reduced pressure to extend the mean free path of gas molecules, reduce contamination, and sustain plasma discharges. The mean free path of a molecule is:

\[ \lambda = \frac{k_B T}{\sqrt{2}\,\pi d^2 P} \]

where \(d\) is the molecular diameter, \(P\) the pressure, \(T\) the temperature, and \(k_B\) Boltzmann’s constant. At atmospheric pressure \(\lambda \approx 70\,\text{nm}\); at \(10^{-3}\,\text{Torr}\) (rough vacuum), \(\lambda \approx 5\,\text{cm}\); at \(10^{-7}\,\text{Torr}\) (high vacuum), \(\lambda \approx 500\,\text{m}\). Thin-film processes span this entire range depending on the mechanism employed.

2.1.1 Vacuum Pump Types

Pressure Range	Pump Type
Atmosphere → 1 Torr	Rotary vane (mechanical)
1 Torr → \(10^{-4}\) Torr	Roots blower, turbomolecular
\(< 10^{-4}\) Torr	Turbomolecular, cryopump, ion pump

Turbomolecular pumps use high-speed spinning blades (up to 90,000 rpm) to impart directional momentum to gas molecules, expelling them toward the roughing pump. They provide clean, oil-free high vacuum and are standard for PVD and CVD reactors.

2.2 Plasma Physics Fundamentals

A plasma is a partially ionised gas consisting of free electrons, positive ions, and neutral species. In semiconductor processing, low-temperature (non-equilibrium) plasmas are sustained by radiofrequency (RF) electric fields at 13.56 MHz (the ISM frequency allocated globally for industrial use).

2.2.1 Plasma Generation

Electron avalanche ionisation is initiated when free electrons gain sufficient energy from the RF field to ionise neutral atoms:

\[ e^- + A \rightarrow A^+ + 2e^- \]

The Paschen curve describes the breakdown voltage \(V_b\) as a function of the product \(P \cdot d\) (pressure × electrode gap). For argon, the minimum breakdown voltage is about 137 V at \(P \cdot d \approx 1\,\text{Torr}\cdot\text{cm}\).

2.2.2 The Debye Length and Plasma Sheath

In a plasma, any surface exposed to the plasma acquires a negative charge (because electrons are more mobile than ions). This repels electrons and attracts ions, forming a sheath — a space-charge region devoid of electrons. The characteristic length over which the plasma shields electric perturbations is the Debye length:

\[ \lambda_D = \sqrt{\frac{\varepsilon_0 k_B T_e}{n_e e^2}} \]

where \(n_e\) is the electron density and \(T_e\) the electron temperature. Typical values in processing plasmas: \(\lambda_D \sim 0.01\text{–}1\,\text{mm}\), \(n_e \sim 10^9\text{–}10^{12}\,\text{cm}^{-3}\), \(T_e \sim 1\text{–}10\,\text{eV}\).

The plasma potential \(V_p\) is positive with respect to any grounded surface. The potential drop across the sheath accelerates ions toward the wafer surface, enabling directional (anisotropic) etching.

2.2.3 DC Bias and Self-Bias

In a capacitively coupled plasma (CCP) reactor with an asymmetric electrode configuration, the smaller powered electrode (on which the wafer sits) develops a self-bias voltage \(V_{dc}\) that is negative relative to the plasma:

\[ \frac{V_1}{V_2} \approx \left(\frac{A_2}{A_1}\right)^q \]

where \(A_1\), \(A_2\) are electrode areas and \(q\) is typically 1–2. Larger self-bias produces more energetic ion bombardment, which drives anisotropic etching.

2.2.4 Plasma Diagnostics

• Langmuir probe: a small metallic probe swept through voltage to measure \(I\text{–}V\) characteristics, yielding \(n_e\), \(T_e\), and \(V_p\).
• Optical emission spectroscopy (OES): monitors emission lines of plasma species for endpoint detection.
• Mass spectrometry: identifies neutral and ionic species in the plasma.

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Chapter 3: Thin Films and Deposition Processes

3.1 Physical Vapor Deposition (PVD)

PVD processes transfer material from a solid or liquid source to a substrate in the vapor phase without chemical reaction. The two dominant PVD techniques are evaporation and sputtering.

3.1.1 Thermal and Electron-Beam Evaporation

In thermal evaporation, a source material is resistively or inductively heated in high vacuum until it evaporates. The vapor pressure must exceed approximately \(10^{-2}\,\text{Torr}\) at the evaporation temperature. For electron-beam (e-beam) evaporation, a focused electron beam (5–10 keV) heats a local spot on the source, avoiding contamination from a resistive heater. Deposition rates are 0.1–10 nm/s.

The deposited film thickness on a planar substrate follows a cosine distribution:

\[ t(r) = t_0 \cos\theta_s \cos\theta_r / r^2 \]

where \(\theta_s\) is the angle from the source normal and \(\theta_r\) the angle at the receiving substrate. Evaporation has poor step coverage (conformal coating of topography) and is limited to materials with sufficiently high vapor pressure.

3.1.2 Sputter Deposition

Sputtering uses energetic ions (typically Ar\(^+\), 100–1000 eV) to physically eject target atoms by momentum transfer. Ejected atoms travel to the substrate and condense as a film. The sputter yield \(S\) is defined as the number of target atoms ejected per incident ion:

\[ S = \frac{C_1 M_s M_t}{(M_s + M_t)^2} \cdot \frac{E_i}{U_s} \]

(Thompson’s simplified model) where \(M_s\), \(M_t\) are ion and target atomic masses, \(E_i\) the ion energy, \(U_s\) the surface binding energy, and \(C_1\) a material constant. Sputter deposition provides better step coverage than evaporation (due to broader angular distribution) and can deposit refractory metals (W, Mo, Ta) and alloys.

Magnetron sputtering adds a magnetic field perpendicular to the electric field above the target, trapping secondary electrons in closed drift orbits. This dramatically increases ionisation efficiency, enabling lower-pressure operation (1–10 mTorr) and higher deposition rates.

Reactive sputtering introduces a reactive gas (N\(_2\), O\(_2\)) to form compound films: TiN (diffusion barriers), TaN (Cu-metallisation barrier), Al\(_2\)O\(_3\) (hard coatings).

3.2 Chemical Vapor Deposition (CVD)

CVD deposits films via chemical reactions of gaseous precursors on or near the heated substrate surface. The key advantage over PVD is conformality — CVD films coat all surfaces (vertical, horizontal, bottom of vias) uniformly when operating in the reaction-rate-limited regime.

3.2.1 CVD Rate-Limiting Regimes

The overall deposition rate is limited by the slowest of:

1. Gas-phase transport (mass-transport limited, high T): weakly temperature-dependent, dependent on gas flow and reactor geometry.
2. Surface reaction (reaction-rate limited, low T): strongly temperature-dependent, \(R \propto \exp(-E_a/k_BT)\).

In surface-reaction-limited regime (desired for uniformity across a batch):

\[ R = A \cdot C_s \cdot \exp\!\left(-\frac{E_a}{k_B T}\right) \]

where \(A\) is a pre-exponential factor and \(C_s\) is the surface reactant concentration.

3.2.2 Atmospheric and Low-Pressure CVD

APCVD (atmospheric pressure CVD) is fast but has poor uniformity due to mass-transport limitations. Used for thick SiO\(_2\) passivation layers.

LPCVD (low pressure CVD, 0.1–10 Torr) operates in the reaction-rate-limited regime, giving excellent wafer-to-wafer and within-wafer uniformity. Processes include:

• Polysilicon: SiH\(_4\) → Si + 2H\(_2\) at 580–650 °C
• Silicon nitride: 3SiH\(_2\)Cl\(_2\) + 4NH\(_3\) → Si\(_3\)N\(_4\) + 6HCl + 6H\(_2\) at 700–800 °C
• TEOS oxide: Si(OC\(_2\)H\(_5\))_4 → SiO\(_2\) + by-products at 650–750 °C

3.2.3 Plasma-Enhanced CVD (PECVD)

PECVD uses plasma to dissociate precursor gases, enabling deposition at 200–400 °C — well below the \(\sim\)900 °C needed for thermal LPCVD. This is critical for back-end-of-line (BEOL) processes where metal interconnects cannot withstand high temperatures. PECVD SiN\(_x\):H (from SiH\(_4\) + NH\(_3\) + N\(_2\)) is widely used as a passivation layer and anti-reflection coating for solar cells. The hydrogen content in PECVD films is significant (5–30 at.%) and influences film stress and etch rates.

3.2.4 Atomic Layer Deposition (ALD)

ALD uses sequential, self-limiting surface reactions to deposit films one atomic layer at a time. A standard cycle:

1. Pulse of precursor A (e.g., trimethylaluminium, TMA) → adsorption to surface OH groups, self-terminating at monolayer.
2. Purge with inert gas.
3. Pulse of reactant B (H\(_2\)O) → reaction with adsorbed TMA, releasing CH\(_4\) and forming Al\(_2\)O\(_3\).
4. Purge.

Growth per cycle (GPC) is 0.1–0.2 nm. ALD gives perfect conformality even in high-aspect-ratio features (HAR > 50:1) and sub-nanometer thickness control. Used for high-\(\kappa\) gate dielectrics (HfO\(_2\), Al\(_2\)O\(_3\)), diffusion barriers (TaN, TiN), and charge-trapping layers in NAND flash.

3.3 Film Characterisation

The four-point probe method measures sheet resistance without contact resistance artifacts. Current is injected through outer probes and voltage sensed at inner probes:

\[ R_\square = \frac{\pi}{\ln 2} \cdot \frac{V}{I} \approx 4.532 \cdot \frac{V}{I} \]

Film thickness is measured by ellipsometry (optical), stylus profilometry, or X-ray reflectometry (XRR). Composition is characterised by XPS, SIMS, or RBS.

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Chapter 4: Plasma Etching Processes

4.1 Wet Etching

Before plasma processes became available, wet (liquid) chemical etching was universal. Common etchants:

• SiO\(_2\): buffered HF (BHF = NH\(_4\)F + HF), etch rate \(\sim\)100 nm/min. Reaction: SiO\(_2\) + 6HF → H\(_2\)SiF\(_6\) + 2H\(_2\)O.
• Silicon: KOH (anisotropic, \(\langle 111 \rangle\) planes etch slowly), or HF/HNO\(_3\)/acetic acid (isotropic).
• Al: phosphoric/acetic/nitric acid mixture (80:5:1).

Wet etching is isotropic (equal etch rates in all directions), so it undercuts mask edges by roughly the etch depth. This limits pattern transfer fidelity for features below \(\sim\)3 µm. Wet etching remains important in MEMS for deep bulk silicon micromachining and in final cleaning steps (RCA clean: SC-1 for particles/organics, SC-2 for metals).

4.2 Dry Etching — Mechanisms

Plasma-based (dry) etching can achieve the anisotropy required for sub-micron patterning. Three distinct mechanisms operate:

1. Physical sputtering: pure momentum transfer, directional, non-selective.
2. Chemical etching: reactive neutrals attack surface, isotropic, selective.
3. Ion-enhanced chemical etching (IECE): synergistic combination — ion bombardment activates the surface toward chemical reaction. Directional AND selective.

The etch rate in IECE is far greater than either mechanism alone (the Coburn–Winters synergy effect). XeF\(_2\) etches silicon at 4 Å/min; Ar\(^+\) bombardment alone gives 2 Å/min; combined, the rate exceeds 80 Å/min.

4.3 Reactive Ion Etching (RIE)

In RIE, the wafer sits on the powered RF electrode. The combination of reactive species and ion bombardment from the plasma sheath provides anisotropic etching. Key process gases:

• Silicon etching: SF\(_6\), CF\(_4\), Cl\(_2\)/HBr
• SiO\(_2\) etching: CHF\(_3\)/O\(_2\), C\(_4\)F\(_8\)/Ar (high selectivity vs. Si)
• Al: BCl\(_3\)/Cl\(_2\)
• III–V: BCl\(_3\), PCl\(_3\)

Etch selectivity is the ratio of etch rates of the target film to the mask (photoresist or hardmask) or the underlying layer. High selectivity (\(> 10:1\)) is needed to avoid damage to adjacent materials.

4.4 Deep RIE and the Bosch Process

For MEMS structures requiring aspect ratios > 10:1 and vertical sidewalls, the Bosch process (patented by Robert Bosch GmbH) alternates:

1. Etch step: SF\(_6\) plasma, isotropic silicon etch, \(\sim\)5–10 s.
2. Passivation step: C\(_4\)F\(_8\) plasma deposits fluorocarbon polymer on all surfaces, \(\sim\)5–8 s.

Ion bombardment on the trench bottom removes the polymer there but not on sidewalls, so etching continues vertically. The cycle leaves characteristic scalloping (\(\sim\)100–300 nm amplitude) on sidewalls. Etch rates reach 10–20 µm/min with aspect ratios > 50:1.

4.5 Etch Uniformity and Loading Effects

Macroloading occurs when the fraction of the wafer covered by the etch target material affects the bulk radical concentration and thus the etch rate. Microloading (aspect-ratio-dependent etching, ARDE) is the decrease in etch rate with increasing aspect ratio due to transport limitations of radicals into deep trenches.

Endpoint detection prevents over-etching. OES monitors characteristic emission from etch products (e.g., SiF\(^*\) at 777 nm for silicon in fluorine plasma). A sharp drop in this signal indicates the target layer is fully etched.

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Chapter 5: Fabrication of Nanostructures

5.1 Top-Down vs. Bottom-Up Approaches

Top-down nanofabrication starts with a bulk material or thin film and removes or patterns material to define nanostructures. Standard photolithography + etching is top-down. As features shrink below \(\sim\)10 nm, limitations arise from photon wavelength, etch mask roughness, and statistical dopant fluctuations.

Bottom-up approaches build nanostructures from atomic or molecular precursors through self-assembly, chemical synthesis, or directed growth. Examples: quantum dots by Stranski–Krastanov growth, carbon nanotubes by CVD, self-assembled monolayers (SAMs), block copolymer lithography.

5.2 Quantum Confinement and Nanoscale Properties

When a semiconductor dimension \(L\) approaches the de Broglie wavelength of electrons \(\lambda_{dB} = h/\sqrt{2m^*E}\) or the exciton Bohr radius, quantum confinement splits continuous bands into discrete energy levels. The energy separation scales as \(1/L^2\) (particle-in-a-box):

\[ E_n = \frac{n^2 \pi^2 \hbar^2}{2 m^* L^2} \]

For GaAs, the Bohr radius is \(\sim\)13 nm; confinement effects become significant for dimensions below 20–30 nm. Quantum wells (2D), quantum wires (1D), and quantum dots (0D) are the three canonical confinement geometries.

5.3 Semiconductor Quantum Dots

Colloidal QDs (CdSe/ZnS, PbS, InP) are synthesised by hot-injection chemistry: organometallic precursors are rapidly injected into a hot surfactant solution (150–350 °C), causing nucleation burst. Growth conditions (time, temperature, ligand) determine final diameter and size distribution (\(\sigma \sim 5\text{–}10\%\)).

Epitaxial QDs (InAs on GaAs) grow by the Stranski–Krastanov mechanism: after a 2D wetting layer (\(\sim\)1.7 ML InAs), strain energy drives 3D island nucleation. Subsequent GaAs capping buries the QDs for device integration (single-photon sources, QD lasers).

5.4 Carbon Nanostructures

Carbon nanotubes (CNTs) are rolled graphene sheets. Single-walled CNTs (SWCNTs) have diameter 0.7–2 nm and exhibit metallic or semiconducting character depending on the chiral vector \((n,m)\): metallic if \(n - m \equiv 0\pmod{3}\), semiconducting otherwise. Band gap scales as \(E_g = 0.9\,\text{eV·nm}/d\).

CVD growth: Fe, Co, or Ni nanoparticle catalysts deposited on a substrate are exposed to CH\(_4\) or C\(_2\)H\(_2\) at 700–1000 °C. Carbon dissolves in the catalyst particle and precipitates as a CNT from the particle surface (tip or base growth model).

Graphene (single-atom-thick carbon lattice, zero-gap semimetal) is produced by chemical vapor deposition on Cu foil at \(\sim\)1000 °C from CH\(_4\)/H\(_2\). After growth, graphene is transferred to target substrates by polymer (PMMA) support + Cu wet etch.

5.5 Nanowires

Semiconductor nanowires (Si, Ge, GaAs, ZnO) are synthesised by the vapor–liquid–solid (VLS) mechanism. A metal catalyst nanoparticle (Au is most common) forms a liquid alloy with the semiconductor feedstock at elevated temperature. The alloy supersaturates, precipitating crystalline nanowire from the solid–liquid interface. Diameter is determined by the catalyst nanoparticle diameter. Growth direction is typically \(\langle 111 \rangle\) for Si and \(\langle 001 \rangle\) for III–V nanowires.

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Chapter 6: Optical Lithography and Its Limits

6.1 Overview of the Lithography Process

Photolithography transfers a pattern from a photomask to a light-sensitive polymer layer (photoresist) on the wafer. The sequence is:

1. Surface preparation: dehydration bake (150–250 °C), HMDS (hexamethyldisilazane) adhesion promotion.
2. Resist coating: spin coating at 1000–5000 rpm, achieving 0.5–3 µm films with < 1% thickness variation.
3. Soft bake (pre-exposure bake): 90–110 °C, removes solvent, densifies resist.
4. Exposure: UV light through a mask exposes regions of the resist.
5. Post-exposure bake (PEB): for chemically amplified resists, drives the acid-catalyzed deprotection reaction.
6. Development: selective dissolution of exposed (positive resist) or unexposed (negative resist) regions.
7. Hard bake: optional, stabilises resist for subsequent etching.

6.2 Resolution Limits — The Rayleigh Criterion

The minimum resolvable feature size (half-pitch) in projection lithography is governed by the Rayleigh criterion:

\[ R = k_1 \frac{\lambda}{\text{NA}} \]

where \(\lambda\) is the exposure wavelength, NA = \(n\sin\theta\) is the numerical aperture of the projection lens (\(n\) is immersion medium refractive index), and \(k_1\) is a process-dependent factor (minimum theoretical value 0.25; practical range 0.3–0.5).

The depth of focus (DOF) is:

\[ \text{DOF} = k_2 \frac{\lambda}{\text{NA}^2} \]

where \(k_2 \approx 0.5\text{–}1\). There is a fundamental trade-off: increasing NA improves resolution but reduces DOF, tightening focus requirements on the wafer stage.

6.3 Wavelength Evolution and Source Technologies

Generation	Source	λ (nm)	Approximate Node
g-line	Hg lamp	436	1 µm
i-line	Hg lamp	365	350 nm
KrF	Excimer laser	248	180 nm
ArF	Excimer laser	193	90 nm
ArF immersion	193 + H\(_2\)O	134 effective	45 nm and below
EUV	Laser-produced Sn plasma	13.5	7 nm and below

6.4 Resolution Enhancement Techniques (RET)

When the feature size approaches the wavelength, diffraction causes proximity effects — features print differently depending on their neighbourhood. RETs compensate:

• Phase-shift masks (PSM): alternating regions of the mask have a 180° phase difference in transmitted light. Destructive interference at edges improves contrast.
• Optical proximity correction (OPC): computational adjustment of mask shapes (serifs, hammerheads, sub-resolution assist features) to pre-compensate for diffraction-induced distortions.
• Illumination engineering: off-axis illumination (annular, dipole, quadrupole) enhances contrast for specific pattern orientations.
• Double/multiple patterning: split features across two (or more) exposures to halve the effective pitch. LELE (litho-etch-litho-etch) and SADP (self-aligned double patterning) are key variants.

6.5 Photoresist Chemistry

Positive photoresists (Novolac/DNQ for i-line; chemically amplified resists, CARs, for KrF/ArF): exposure generates a photoacid (in CARs); PEB drives acid-catalyzed deprotection of blocked polymer groups, increasing solubility in the aqueous base developer.

Negative photoresists: exposure crosslinks polymer, rendering it insoluble. Used for lift-off processes and some specialty applications. Modern negative-tone development (NTD) of positive-tone CARs uses organic solvent developers to achieve negative-tone patterns with positive resist materials, improving resolution.

The contrast (or gamma, \(\gamma\)) of a resist characterises how sharply the thickness changes with log-exposure dose:

\[ \gamma = \frac{1}{\log(E_{f}/E_i)} \]

High contrast (\(\gamma > 3\)) gives sharp pattern edges and reduces sensitivity to standing waves and dose variations.

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Chapter 7: Nanopatterning

7.1 Electron Beam Lithography (EBL)

EBL uses a focused electron beam (typically 50–100 keV) raster-scanned over a resist-coated substrate. Resolution is not wavelength-limited (the de Broglie wavelength of 100 keV electrons is 0.0039 nm); instead, it is limited by:

• Forward scattering in the resist: beam broadening increases with resist thickness.
• Backscattering from the substrate: electrons scattered back from the substrate expose resist far (1–10 µm) from the beam, creating the proximity effect. Proximity effect correction (PEC) adjusts dose across patterns computationally.

EBL achieves sub-10 nm feature sizes in thin PMMA resist (30–50 nm). It is serial (slow), typically used for mask writing, research prototyping, and photomask fabrication, not for high-volume manufacturing.

Common EBL resists:

• PMMA (polymethylmethacrylate): positive, high resolution, low sensitivity.
• HSQ (hydrogen silsesquioxane): negative, inorganic, extreme resolution (\(\sim\)5 nm).
• ZEP 520A: positive, better sensitivity than PMMA, moderate resolution.

7.2 Focused Ion Beam (FIB)

FIB uses a liquid metal ion source (LMIS, typically Ga\(^+\)) focused to \(\sim\)5 nm. Applications:

• Direct milling: sputter-removal of material without resist for cross-section preparation, circuit edit, TEM sample prep.
• FIB-assisted deposition: inject organometallic precursor gas (e.g., W(CO)\(_6\)) near the beam; ion-induced decomposition deposits W locally.
• Dual-beam FIB-SEM: simultaneous scanning electron microscope column for real-time imaging during milling.

7.3 Nanoimprint Lithography (NIL)

NIL mechanically stamps a topographically patterned mold (or template) into a viscous resist layer. Two principal variants:

1. Thermal NIL (hot embossing): thermoplastic polymer (PMMA) is heated above \(T_g\) (\(\sim\)105 °C), template pressed in, cooled, then released. Achieves features down to \(\sim\)10 nm.
2. UV-NIL (step-and-flash imprint, S-FIL): low-viscosity UV-curable monomer is dispensed on wafer; transparent quartz template pressed in; UV exposure polymerises the monomer; template released.

NIL does not suffer from diffraction limits and achieves sub-10 nm resolution at low cost per wafer, but defect density (template contamination, particle inclusions) and template lifetime are challenges.

7.4 Self-Assembled Monolayers and Block Copolymers

SAMs form by spontaneous chemisorption of bifunctional molecules (e.g., alkanethiols on Au, organosilanes on SiO\(_2\)) from solution. The head group bonds to the surface; the tail controls surface energy and chemistry. SAMs are used as ultra-thin etch resists, surface functionalisation layers for selective deposition, and templates for molecular electronics research.

Block copolymer (BCP) lithography exploits microphase separation of chemically distinct polymer blocks (e.g., PS-b-PMMA) into periodic nanodomains (cylinders, lamellae, spheres) with periodicity 10–50 nm — below the EBL resolution routinely achievable at high throughput. The PMMA cylinders can be selectively removed (UV + acetic acid), leaving a PS mask for pattern transfer. Graphoepitaxy uses topographic guide features to orient and register BCP domains for circuit-compatible patterns.

7.5 Scanning Probe Lithography

Dip-pen nanolithography (DPN) uses an AFM tip coated with ink molecules to write patterns by direct transfer via water meniscus. Features down to \(\sim\)15 nm are achievable. Multiplex DPN (massively parallel cantilever arrays) improves throughput.

Tip-induced oxidation (local anodic oxidation, LAO) uses a conductive AFM tip in contact mode to locally oxidise Si or Ti surfaces under controlled humidity, writing oxide lines \(\sim\)10 nm wide usable as etch masks.

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Chapter 8: Device Fabrication — Junction Formation

8.1 p–n Junction Fundamentals

A p–n junction is formed at the interface between p-type (acceptor-doped) and n-type (donor-doped) semiconductor. At equilibrium, the built-in potential is:

\[ V_{bi} = \frac{k_B T}{q} \ln\!\left(\frac{N_A N_D}{n_i^2}\right) \]

where \(N_A\) is the acceptor concentration, \(N_D\) the donor concentration, and \(n_i\) the intrinsic carrier concentration. For silicon at 300 K, \(n_i = 1.5 \times 10^{10}\,\text{cm}^{-3}\).

Minority-carrier recombination in the depletion region is described by Shockley–Read–Hall (SRH) theory:

\[ U = \frac{np - n_i^2}{\tau_p(n + n_1) + \tau_n(p + p_1)} \]

where \(\tau_n\), \(\tau_p\) are the minority-carrier lifetimes, and \(n_1\), \(p_1\) are equilibrium concentrations at the trap energy. High-quality junctions require long lifetimes (low defect density), which is why crystal quality and contamination control are so critical.

8.2 Thermal Diffusion

Thermal diffusion is the oldest method of junction formation. Dopant atoms are introduced at the surface and driven into the semiconductor by high-temperature annealing. The process is governed by Fick’s second law:

\[ \frac{\partial C}{\partial t} = D \frac{\partial^2 C}{\partial x^2} \]

where \(C(x,t)\) is the dopant concentration, \(D\) the diffusion coefficient, \(x\) the depth, and \(t\) time.

The diffusivity \(D\) is thermally activated:

\[ D = D_0 \exp\!\left(-\frac{E_a}{k_B T}\right) \]

For boron in silicon: \(D_0 \approx 0.76\,\text{cm}^2/\text{s}\), \(E_a \approx 3.46\,\text{eV}\). At 1100 °C, \(D_B \approx 4 \times 10^{-13}\,\text{cm}^2/\text{s}\).

8.2.1 Two-Step Diffusion

In practice, diffusion is a two-step process:

Step 1 — Predep (constant surface concentration): The surface is held at the solid-solubility limit \(C_s\) by exposure to a dopant source (gas or doped glass). The profile is a complementary error function:

\[ C(x,t_1) = C_s \,\text{erfc}\!\left(\frac{x}{2\sqrt{D t_1}}\right) \]

Total dose introduced: \(Q = \frac{2C_s}{\sqrt{\pi}} \sqrt{D t_1}\).

Step 2 — Drive-in (constant total dose): The dopant source is removed; the wafer is annealed at a different temperature to redistribute the dopant, giving a Gaussian profile:

\[ C(x,t_2) = \frac{Q}{\sqrt{\pi D t_2}} \exp\!\left(-\frac{x^2}{4 D t_2}\right) \]

The junction depth \(x_j\) is where \(C(x_j) = C_{\text{background}}\) (the substrate doping).

8.3 Ion Implantation

Ion implantation is the dominant junction-formation technique in modern CMOS. Ions are accelerated to energies of 1–200 keV, impinge on the silicon surface, and are stopped by nuclear and electronic collisions.

8.3.1 Range and Straggle

The average depth at which ions stop is the projected range \(R_p\); the spread around this depth is the projected straggle \(\Delta R_p\). The as-implanted profile (before anneal) is approximately Gaussian:

\[ C(x) = \frac{\Phi}{\sqrt{2\pi}\,\Delta R_p} \exp\!\left(-\frac{(x - R_p)^2}{2\Delta R_p^2}\right) \]

where \(\Phi\) is the implant dose (ions/cm\(^2\)).

The SRIM/TRIM (Stopping and Range of Ions in Matter) Monte Carlo code is the standard tool for predicting \(R_p\) and \(\Delta R_p\).

8.3.2 Implant Damage and Annealing

High-dose implantation (>\(10^{14}\,\text{cm}^{-2}\)) can amorphise the silicon (all atoms displaced from lattice positions). Upon thermal annealing (solid-phase epitaxial regrowth, SPER), the amorphous layer recrystallises from the crystal-amorphous interface, restoring lattice order. Key concern: transient enhanced diffusion (TED) — implant-generated interstitials form clusters that dissolve during anneal, releasing interstitials that temporarily enhance diffusion. TED causes boron to diffuse 10–100× faster than predicted by equilibrium \(D\), creating deeper junctions than intended.

Spike annealing (rapid thermal annealing with very short time at peak temperature, e.g., 1050 °C for < 1 s) and flash/laser annealing (millisecond or nanosecond heating) limit TED by minimising interstitial diffusion time while still fully activating dopants.

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Chapter 9: Device Fabrication — Oxide Growth

9.1 Thermal Oxidation of Silicon

The growth of SiO\(_2\) on silicon by thermal oxidation is the cornerstone of silicon IC technology, providing:

• Gate dielectric in MOSFETs.
• Field oxide for isolation.
• Passivation and masking layers.

The reaction consumes silicon: 44 nm of SiO\(_2\) grown requires \(\sim\)19 nm of silicon consumed (volume ratio Si/SiO\(_2\) = 0.44). The Si–SiO\(_2\) interface is exceptional: interface trap density \(D_{it} < 10^{10}\,\text{cm}^{-2}\text{eV}^{-1}\) is routinely achievable, enabling MOSFET gate control.

9.2 The Deal–Grove Model

The Deal–Grove model (B. E. Deal and A. S. Grove, 1965) describes the oxidation kinetics quantitatively. Oxidant (O\(_2\) or H\(_2\)O) must:

1. Transport through the gas phase to the oxide surface.
2. Diffuse through the growing oxide (limited by diffusivity \(D_{ox}\) in SiO\(_2\)).
3. React at the Si–SiO\(_2\) interface.

Under steady-state flux balance, the oxide thickness \(x\) as a function of time \(t\) obeys:

\[ x^2 + A x = B(t + \tau) \]

where:

• \(B = \frac{2 D_{ox} C^*}{N}\) is the parabolic rate constant (units: cm\(^2\)/s), dominated by diffusion through the oxide. \(C^*\) is the equilibrium oxidant concentration in SiO\(_2\), \(N\) the oxidant density in SiO\(_2\).
• \(B/A = \frac{k_s C^*}{N}\) is the linear rate constant (units: cm/s), controlled by the interface reaction rate \(k_s\).
• \(\tau = (x_0^2 + A x_0)/B\) accounts for any initial oxide \(x_0\).

9.2.1 Rate Constants

For dry oxidation (O\(_2\)) at 1000 °C:

• \(B = 3.8 \times 10^{-3}\,\mu\text{m}^2/\text{hr}\)
• \(B/A = 1.2 \times 10^{-1}\,\mu\text{m}/\text{hr}\)

For wet oxidation (H\(_2\)O) at 1000 °C:

• \(B = 2.87 \times 10^{-1}\,\mu\text{m}^2/\text{hr}\)
• \(B/A = 7.2 \times 10^{-1}\,\mu\text{m}/\text{hr}\)

Wet oxidation is \(\sim\)10× faster because the solubility and diffusivity of H\(_2\)O in SiO\(_2\) are both much higher than those of O\(_2\). Dry oxidation produces denser, higher-quality oxides used for gate dielectrics; wet oxidation grows thick field oxides rapidly.

9.2.2 Thin Oxide Anomaly

The Deal–Grove model predicts zero initial growth rate, but experimentally thin oxides (\(< 25\,\text{nm}\)) grow faster than predicted. This is attributed to stress effects, direct tunnelling of oxidant, and space-charge effects near the interface that enhance the local oxidant flux.

9.3 LOCOS and STI Isolation

LOCOS (Local Oxidation of Silicon): a pad oxide and Si\(_3\)N\(_4\) layer are deposited; the nitride is patterned to expose field regions; thermal oxidation grows thick field oxide (500 nm–1 µm) only in exposed areas. The nitride prevents oxidation beneath it. The transition region between field oxide and active area has a characteristic shape called the bird’s beak — lateral oxide growth under the nitride edge consumes active area, a serious problem for sub-0.5 µm features.

STI (Shallow Trench Isolation): shallow trenches (200–500 nm deep) are etched into silicon, lined with a thermal oxide (stress relief), filled with HDP-CVD (high-density plasma CVD) SiO\(_2\), and planarised by chemical mechanical planarisation (CMP). STI eliminates the bird’s beak problem and is the standard isolation technique for all CMOS below 0.25 µm.

9.4 High-κ Gate Dielectrics

As the SiO\(_2\) gate dielectric scaled below \(\sim\)1.5 nm (for 45 nm node and below), direct quantum-mechanical tunnelling of electrons through the oxide became unacceptably large (\(> 1\,\text{A/cm}^2\)). High-permittivity (high-\(\kappa\)) dielectrics — most prominently HfO\(_2\) (\(\kappa \approx 25\)) — allow a physically thicker layer with the same equivalent oxide thickness (EOT):

\[ \text{EOT} = t_{high-\kappa} \cdot \frac{\kappa_{SiO_2}}{\kappa_{high-\kappa}} = t_{HfO_2} \cdot \frac{3.9}{25} \approx 0.156\, t_{HfO_2} \]

A 3 nm HfO\(_2\) film provides EOT \(\approx\) 0.47 nm while suppressing tunnelling current by orders of magnitude. High-\(\kappa\) dielectrics are deposited by ALD, paired with metal gate electrodes (TiN, TaN) to eliminate the threshold voltage shift caused by poly-Si gate depletion.

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Chapter 10: Transistor and CMOS Fabrication

10.1 MOSFET Structure and Operation

The MOSFET (metal-oxide-semiconductor field-effect transistor) is the fundamental building block of digital ICs. The n-channel MOSFET (nMOS) consists of a p-type silicon body with n\(^+\) source and drain regions, separated by a thin gate oxide and gate electrode. The threshold voltage is:

\[ V_T = \phi_{ms} - \frac{Q_{ox}}{C_{ox}} + 2\phi_F + \frac{\sqrt{2\varepsilon_s q N_A (2\phi_F)}}{C_{ox}} \]

where \(\phi_{ms}\) is the work function difference between gate and semiconductor, \(Q_{ox}\) the oxide charge, \(C_{ox} = \varepsilon_{ox}/t_{ox}\) the gate capacitance per unit area, \(\phi_F = (k_BT/q)\ln(N_A/n_i)\) the bulk Fermi potential, and \(\varepsilon_s\) the silicon permittivity.

The drain current in saturation is:

\[ I_D = \frac{\mu_n C_{ox}}{2} \cdot \frac{W}{L}(V_{GS} - V_T)^2 \]

where \(W\) is channel width, \(L\) gate length, and \(\mu_n\) the electron mobility.

10.2 CMOS Process Flow Overview

CMOS (complementary MOS) integrates both n-channel and p-channel MOSFETs on the same wafer. The basic process flow (for n-well CMOS on p-type substrate) is:

Step 1: Well Formation

Phosphorus or arsenic implant into n-well regions (defines pMOS location); boron into p-well (defines nMOS body). Drive-in at 1100–1200 °C for 2–4 hr forms wells 2–3 µm deep.

Step 2: Shallow Trench Isolation (STI)

Trench etch (plasma, \(\sim\)350 nm), thermal liner oxide (\(\sim\)10 nm), HDP-CVD SiO\(_2\) fill, CMP planarisation.

Step 3: Gate Stack Formation

• Gate oxide: thermal dry oxidation or ALD HfO\(_2\) (at 45 nm node and below).
• Gate electrode: LPCVD polysilicon (legacy) or ALD/PVD metal gate (TiN/TaN).
• Gate patterning: DUV lithography + RIE (HBr/Cl\(_2\) for poly, or fluorine-based for metal gate).

Step 4: Extension and Halo Implants

Lightly doped drain (LDD) / source-drain extension (SDE) implants: low-energy, high-dose implants (\(\sim\)1–5 keV, \(10^{14}\text{–}10^{15}\,\text{cm}^{-2}\)) self-aligned to the gate. Pocket/halo implants (opposite type, angled) suppress short-channel effects.

Step 5: Spacer Formation

LPCVD Si\(_3\)N\(_4\) or PECVD SiO\(_2\) deposited conformally, then anisotropically etched back to leave spacers on gate sidewalls. Spacer width \(\sim\)50–100 nm defines the offset for deep S/D implants.

Step 6: Source/Drain Implants and Activation

High-dose, high-energy implant (\(10^{15}\text{–}10^{16}\,\text{cm}^{-2}\)) for n\(^+\) (As/P) and p\(^+\) (B) regions, followed by rapid thermal anneal (RTA) at 1000–1075 °C (spike) for activation and damage removal.

Step 7: Silicide Formation (SALICIDE)

Self-aligned silicide (SALICIDE): sputter-deposit Ti or Ni metal (\(\sim\)10 nm) over entire wafer; rapid thermal anneal causes metal to react with exposed silicon (source, drain, poly gate) to form low-resistivity TiSi\(_2\) or NiSi\(_2\); selective wet etch (H\(_2\)O\(_2\)/H\(_2\)SO\(_4\)) removes unreacted metal from oxide/nitride surfaces; optional second anneal completes silicidation.

Sheet resistance of NiSi: \(\sim\)3 Ω/□, vs. \(\sim\)50 Ω/□ for n\(^+\) polysilicon — critical for minimising series resistance at contact regions.

Step 8: Pre-Metal Dielectric (PMD) and Contact Formation

PECVD or HDP-CVD SiO\(_2\) (doped with phosphorus and boron — BPSG) is deposited and CMP planarised. Contact holes are etched (C\(_4\)F\(_8\)/Ar RIE), tungsten CVD fills the contacts (TiN/Ti adhesion/barrier layer first), CMP removes excess W.

Step 9: Back-End-of-Line (BEOL) Interconnect

Multiple metal layers (Al in older nodes; Cu in 0.18 µm and below) connect devices. Cu interconnect uses the dual-damascene process:

1. Deposit low-\(\kappa\) dielectric (SiOF, CDO, or porous SiCOH).
2. Pattern and etch via + trench in one combined litho-etch sequence.
3. PVD TaN/Ta diffusion barrier + Cu seed layer.
4. Electroplated Cu fill.
5. CMP to remove overburden Cu.
6. SiCN or SiN cap layer (Cu diffusion barrier).

Cu resistivity (\(1.7\,\mu\Omega\cdot\text{cm}\)) is lower than Al (\(2.7\,\mu\Omega\cdot\text{cm}\)), reducing RC delay; but Cu contaminates silicon readily, requiring complete barrier encapsulation.

10.3 Short-Channel Effects and Device Scaling

Scaling is the systematic reduction of all device dimensions (gate length, oxide thickness, junction depth, supply voltage) to improve performance and density. The ITRS/IRDS (International Technology Roadmap for Semiconductors) has guided scaling for decades.

Key short-channel effects (SCEs) encountered as \(L\) shrinks:

• Drain-induced barrier lowering (DIBL): drain field lowers the source-channel potential barrier, reducing \(V_T\) at high \(V_{DS}\).
• Subthreshold swing degradation: ideal subthreshold slope 60 mV/decade; SCEs increase this, raising off-state leakage.
• Gate oxide tunnelling: direct tunnelling through ultra-thin SiO\(_2\) — mitigated by high-\(\kappa\) dielectrics.
• Velocity saturation and carrier heating: at high fields, carrier drift velocity saturates at \(v_{sat} \approx 10^7\,\text{cm/s}\) in Si; \(I_D\) becomes proportional to \((V_{GS} - V_T)\) rather than \((V_{GS}-V_T)^2\).

FinFET (Tri-gate) geometry (gate wrapping on three sides of a thin silicon fin) dramatically improves electrostatic control, reducing SCEs. Intel introduced FinFETs at 22 nm in 2012; all sub-22 nm nodes use FinFET or gate-all-around (GAA) nanosheet transistors.

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Chapter 11: Thin Film Device Fabrication

11.1 Thin Film Transistors (TFTs)

A TFT differs from a bulk MOSFET in that both the channel semiconductor and the gate insulator are deposited thin films — there is no monocrystalline silicon substrate required. This enables fabrication on glass, plastic, or any substrate at relatively low temperatures.

Applications: active-matrix LCD and OLED displays (one TFT per pixel), large-area sensors, flexible electronics, and paper-like displays.

11.1.1 Amorphous Silicon TFTs (a-Si:H TFTs)

Hydrogenated amorphous silicon (a-Si:H) deposited by PECVD (from SiH\(_4\)/H\(_2\) at 150–350 °C) is the workhorse material for large-area TFTs. The random network structure introduces mid-gap dangling bond states (density \(\sim 10^{16}\,\text{cm}^{-3}\)) that are partially passivated by hydrogen, reducing the active trap density to \(\sim 10^{15}\,\text{cm}^{-3}\). Electron mobility: \(\mu_e \approx 0.5\text{–}1\,\text{cm}^2/\text{V}\cdot\text{s}\) (much lower than crystalline Si at \(\sim\)1400 cm\(^2\)/V·s due to disorder scattering and trap filling).

The inverted staggered (bottom-gate) structure is standard:

1. Gate metal (Cr, Mo, or Al) sputtered and patterned on glass substrate.
2. Gate dielectric: PECVD SiN\(_x\) (\(\sim\)300 nm).
3. a-Si:H channel layer (\(\sim\)100 nm) PECVD.
4. n\(^+\) a-Si:H contact layer (\(\sim\)50 nm) PECVD.
5. Source/drain metal (Cr/Al) sputtered and patterned.
6. Etch-back of n\(^+\) layer between S and D (channel etch-stop or back-channel-etch variant).
7. Passivation: PECVD SiN\(_x\).

11.1.2 Poly-Silicon TFTs (LTPS TFTs)

Low-temperature poly-silicon (LTPS) is produced by laser crystallisation of a-Si:H films using an excimer laser (XeCl, 308 nm). The laser pulse (20–50 ns) melts the a-Si layer and recrystallises it as poly-Si with grain sizes of 0.3–1 µm without damaging the glass substrate. Mobility: \(\mu_e \approx 100\text{–}200\,\text{cm}^2/\text{V}\cdot\text{s}\), enabling peripheral driver circuits to be integrated on the same glass panel.

Solid-phase crystallisation (SPC) at 600 °C for many hours is an alternative for glass substrates but produces smaller grains and lower mobility than laser crystallisation.

11.1.3 Metal Oxide TFTs

Amorphous IGZO (indium-gallium-zinc oxide) TFTs (Hosono group, 2004) combine:

• High electron mobility (\(\sim\)10–50 cm\(^2\)/V·s) due to large, overlapping s-orbitals of heavy metal cations.
• Good uniformity over large area by sputtering.
• Low processing temperature (\(< 350\,^\circ\)C), compatible with flexible substrates.
• Near-zero off-current due to wide band gap (\(\sim\)3.2 eV).

IGZO TFTs are used in all large-format (> 50 inch) LCD panels and high-resolution OLED displays due to their combination of mobility, uniformity, and low-temperature processability.

11.2 Thin Film Solar Cells

11.2.1 Amorphous Silicon Solar Cells

p-i-n structured a-Si:H cells: the large density of defects in a-Si:H makes conventional pn-junction cells ineffective (minority carrier diffusion length \(\ll\) film thickness). Instead, an intrinsic (i) layer between p and n layers allows photocarriers to be collected by the built-in drift field.

The Staebler–Wronski effect is the metastable degradation of a-Si:H device efficiency under illumination (from light-induced creation of dangling bonds), stabilising at \(\sim\)70–80% of initial efficiency. Multi-junction (tandem) cells using a-Si:H / µc-Si:H (\(\mu\)morph) or a-Si:H/a-SiGe:H improve both absorption and stability.

11.2.2 CdTe and CIGS Solar Cells

CdTe (band gap 1.45 eV, near-ideal for single-junction solar conversion): CdS/CdTe thin film cells are deposited by close-space sublimation or CSS. Activation treatment with CdCl\(_2\) (recrystallisation and grain boundary passivation) is essential. Commercial module efficiencies of 18–22% are achieved.

CIGS (Cu(In,Ga)Se\(_2\)): quaternary compound semiconductor, band gap tunable from 1.0 eV (CIS) to 1.7 eV (CGS) by Ga/In ratio. Deposited by co-evaporation or selenisation of metal precursors. Record cell efficiencies of 23.6% have been achieved in the laboratory. Buffer layer: n-type CdS (\(\sim\)50 nm) or Zn(O,S) by CBD (chemical bath deposition).

11.2.3 Perovskite Solar Cells

Metal halide perovskites (ABX\(_3\), e.g., CH\(_3\)NH\(_3\)PbI\(_3\), MAPbI\(_3\)) have emerged as a revolutionary thin-film solar cell material since 2012. Properties: direct band gap (\(\sim\)1.6 eV, tunable by composition), long carrier diffusion lengths (1–10 µm in single crystals), high absorption coefficient (\(\sim 10^5\,\text{cm}^{-1}\)), and solution processability.

Fabrication methods: spin-coating from DMF/DMSO solution (1-step or 2-step), vapour deposition, or blade coating. Certified single-junction efficiencies have exceeded 26% (2024).

Key stability challenges: moisture sensitivity (MAPbI\(_3\) degrades in air), thermal instability (\(> 85\,^\circ\)C), and light-induced halide segregation in mixed-halide compositions. Encapsulation and compositional engineering (FA/MA/Cs mixed-cation, I/Br mixed-halide, 2D/3D graded structures) address these issues.

11.3 MEMS Technology

MEMS (Micro-Electro-Mechanical Systems) combine mechanical structures (beams, membranes, gears, resonators) with microelectronics, fabricated using IC-compatible processes.

11.3.1 Surface Micromachining

Suspended structures are built above the substrate by depositing, patterning, and selectively etching sacrificial layers. Standard process (PolyMUMPs):

1. Silicon nitride isolation layer on substrate.
2. First poly-Si layer (Poly0): structural or interconnect.
3. First phosphosilicate glass (PSG) sacrificial layer.
4. Second poly-Si layer (Poly1, structural).
5. Second PSG sacrificial layer.
6. Third poly-Si layer (Poly2, structural).
7. Metal (Au or Al) for contacts/reflectors.
8. Release etch: HF vapour or 49% HF liquid dissolves all PSG, freeing suspended Poly1/Poly2 structures.

Stiction (adhesion of released structures to substrate) is a major fabrication challenge; addressed by critical-point drying (CPD), freeze drying, or anti-stiction coatings (SAM or fluorocarbon).

11.3.2 Bulk Micromachining

Deep features (hundreds of µm) are etched into the silicon substrate itself using:

• KOH anisotropic etching: selective on crystal orientation. \(\langle 111 \rangle\) planes etch \(\sim\)400× slower than \(\langle 100 \rangle\). Produces V-grooves (54.7° sidewall angle), membranes, through-wafer holes.
• Bosch DRIE: produces high-aspect-ratio features with vertical sidewalls, used for pressure sensor membranes, microfluidic channels, accelerometer proof masses, gyroscopes.

11.3.3 Wafer Bonding

Separate wafers are joined to form 3D MEMS structures or to encapsulate cavities. Methods:

• Anodic bonding: glass wafer (Corning 7740) bonded to Si at 400 °C by applying 800–1000 V. Na\(^+\) ions migrate away from the interface, leaving a depletion layer that drives oxide bond formation across the interface.
• Fusion bonding: Si–Si or SiO\(_2\)–Si bonded by RCA-cleaned surfaces, contact under pressure, and anneal at 800–1100 °C. Strong covalent bond after anneal.
• Eutectic bonding: Au–Si at 363 °C, or Au–Sn at 280 °C — useful for hermetic sealing at lower temperatures.

11.4 Nanoelectronic Device Fabrication

11.4.1 Silicon Nanowire FETs

Gate-all-around (GAA) silicon nanowire FETs offer ultimate electrostatic control (all four sides gated). Fabrication by a top-down approach:

1. Thin silicon-on-insulator (SOI) wafer.
2. Electron-beam lithography to define nanowire (\(\sim\)10 nm wide, \(\sim\)5 nm thick).
3. Anisotropic etching.
4. ALD gate dielectric (\(\sim\)3 nm HfO\(_2\)).
5. ALD/CVD TiN metal gate.
6. Source/drain doping by ion implantation at low energy.

Intel’s “RibbonFET” and Samsung/TSMC’s nanosheet transistor (3 nm node, 2022) are commercial realizations of stacked nanowire/nanosheet GAA FETs.

11.4.2 Resistive Switching Memory (RRAM)

RRAM cells consist of a metal–insulator–metal (MIM) stack. Applying a voltage forms or dissolves a conductive filament (typically an oxygen vacancy channel in HfO\(_2\), TaO\(_x\), or TiO\(_2\)) through the insulator, switching the cell between high-resistance state (HRS, “0”) and low-resistance state (LRS, “1”). Switching voltages: 1–2 V; cell size can be < 4F\(^2\). Fabrication requires only standard PVD/ALD and BEOL processing, enabling 3D monolithic integration over CMOS logic.

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Summary of Key Equations

Below is a consolidated reference for the most important quantitative relationships covered in this course.

Equation	Description
\(k_0 = C_s/C_l\)	Segregation coefficient (crystal growth)
\(\lambda_D = \sqrt{\varepsilon_0 k_B T_e / n_e e^2}\)	Plasma Debye length
\(R = k_1 \lambda/\text{NA}\)	Rayleigh resolution limit
\(\partial C/\partial t = D\,\partial^2 C/\partial x^2\)	Fick’s second law (diffusion)
\(x^2 + Ax = B(t+\tau)\)	Deal-Grove oxidation model
\(D = D_0\exp(-E_a/k_BT)\)	Arrhenius diffusivity
\(V_{bi} = (k_BT/q)\ln(N_A N_D/n_i^2)\)	Built-in junction voltage
\(U = (np - n_i^2)/[\tau_p(n+n_1)+\tau_n(p+p_1)]\)	SRH recombination rate
\(\text{EOT} = t_{hk}\,(\kappa_{SiO_2}/\kappa_{hk})\)	Equivalent oxide thickness
\(E_n = n^2\pi^2\hbar^2/(2m^*L^2)\)	Quantum confinement energy levels

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